BIOMIMETIC CORTICAL NANOCIRCUITS - Bio-Inspired and Nanoscale Integrated Computing - page 468

17.5. CURRENT PREDICTION RESEARCH

This section describes prediction research regarding the feasibility of a CMOS
synthetic cortex [2], including flip-chip technology to gain additional vertical
interconnections between two integrated circuit dies. First, we predict the size
of a single neuron, and then predict the space occupied by the 100 billion
neurons in the cortex. Finally we approach the problem of interconnectivity,
predicting the connections possible to a CMOS core, including the use of flip-chip
technology.

17.5.1. Predicted CMOS Neuron Size
We have predicted the size of a single neuron, absent any interconnections or
learning capability, and projected the physical size over time until 2019 using the
International Technology Roadmap for Semiconductors [78]. Our assumptions of
neural size were based on electronic neurons found in the literature and our own
synapse design, and we predict a significant part of an entire office being required
to house the neurons in a synthetic neural cortex in 2021. We begin our CMOS
prediction using typical biomimetic neural electronic circuits (the Liu-Frenzel
neuron [26] and Boahen's neuron [1] are examples) and extend the prediction using
our own synapse described in Section 17.4 as a measure of synaptic complexity.
The simplest possible synaptic structure is a single MOS transistor. However,
additional transistors would be required to model memory, learning, neurotrans-
mitters, the refactory period, and other phenomena that complicate the behavior
of the synapse. While the biological mechanisms underlying the synaptic behavior
are complex and not completely understood, we are making an assumption that
charge storage can be used to model a wide range of phenomena, like the influence
of neurotransmitter concentrations and the impact of learning. Additional
elements can be used to model dynamic behavior such as the refactory period.
Therefore, our estimate of synaptic complexity at this point is a simple order of
magnitude more complex than the simplest synapse, or 10 transistors. The custom
electronic synapses in the literature that do not contain significant learning
mechanisms, with the exception of the research by Hynna and Boahen [25] fall
well under this estimate. The prediction given here ignores dendritic computations
that could contribute significantly to neural complexity [83], ignores calcium
spiking mechanisms in the dendritic arbor, and ignores learning mechanisms.
Because the neuron designs we chose were fairly simplistic, we estimated that
10 7 neurons could fit onto a single die in 2019. Even today, we estimate that 10 4
neurons could fit on a single die.
Let c init be the number of transistors per chip possible in 2006 [84], and c fin be
the number of transistors predicted to be possible per chip for 2021, 15 years from
2006. c init =10 9 transistors per chip and

c fin ¼ c init w M transistors = chip ; ð 17 : 1 Þ