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20 V pulsing
120
40
V DS = 1 V
"ON"
90
30
20
60
10
30
"OFF"
0
0
+20 V pulsing
0
500
1000
1500
2000
0
10
20
20
10
Gate voltage (V)
Time (s)
(a)
(b)
Figure 11.14. (a) I D vs. V G curve for a silicon nanowire with a F-decorated oxide
surface recorded at V DS of +1V, showing a large hysteresis for different gate voltage
sweeping directions. (b) The memory performance of the silicon nanowire-FET
device showing distinct and stable ON/OFF state with write/erase operation. After
each +20V gate pulsing (write) or 20V pulsing (erase) for 5 s, the device state was
consecutively read 50 times with drain current at V DS of +1V.
realize large-scale integration for functional computing. In contrast, it was shown
that molecules can be employed to change the behavior of silicon through surface
grafting, instead of implementing switching themselves. This provides not only a
new mechanism to enhance existing silicon-based process technologies but also a
new modulation technology to implement silicon nanowire-based devices.
ACKNOWLEDGMENTS
We thank our collaborators and lab members for their contributions to the work
described in this chapter; many if their names are cited in the references. The JMT
program has been generously supported by DARPA and to a lesser extent by the
ONR and AFOSR.
REFERENCES
1. J. M. Tour. Molecular Electronics: Commercial Insights, Chemistry, Devices, Archi-
tecture and Programming. Singapore: World Scientific, 2003.
2. G. Cuniberti, G. Fagas, and K. Richter. Introducing Molecular Electronics: A Brief
Overview (Lecture Notes In Physics) New York: Springer, 2005.
3. J. R. Heath, et al. A defect-tolerant computer architecture: opportunities for
nanotechnology. Science, 280(5370): p 1716, 1998.
4. M. Mishra and S. C. Goldstein. Scalable defect tolerance for molecular electronics. In:
First Workshop on Non Silicon Computing, 2002.
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