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11.5.2. Molecular Grafting on Intrinsic Silicon Nanowires
Semiconductor nanowires [54, 64, 100, 101], including silicon nanowires, are
promising as building blocks of nanoscale circuits, in particular those based on
crossbar arrays addressed above [53, 78, 102, 103]. Because their carrier mobility is
critical to the circuit performance, considerable efforts have been devoted to
improving silicon nanowire performance [104, 105] with doping. However,
Fernandez-Serra et al. [106] found that uniform doping may not be achievable
in ultra small structures like silicon nanowires. As devices reach the sub-20-nm-
sized regime, variations in doping profiles becomes a severe problem thereby
generating inconsistencies between devices. Recent work done on ultra-thin
silicon-on-insulator (SOI) revealed that its electronic conduction is determined
not by bulk dopant but by the interaction of surface/interface electronic energy
levels with the bulk band structure [87].
We have demonstrated that by controlling surface state densities with a very
simple and rapid aqueous fluoride ion treatment, excellent electronic operation
can be achieved on intrinsic silicon nanowires without bulk doping, thereby taking
advantage of the increase in surface-to-volume ratios in these diminutive struc-
tures. Forming a fluoride-decorated (F-decorated) oxide surface significantly
increases the conductivity and the mobility by more than three orders of
magnitude over the oxide-free H-passivated surface. This provides a methodology
that might sidestep the difficult-to-control impurity doping of nanodevices. Figure
11.13a shows the structure diagram of the fabricated silicon nanowire-FET test
devices; Figure 11.13b shows a typical SEM image of the devices. Figure 11.13c
illustrates the entire sequence: oxide-coated silicon nanowire to fluoride-decorated
oxide coatings to H-passivated structures.
We also found that the silicon nanowire devices with F-decorated oxide
surfaces exhibited large hystereses during the gate voltage sweeps, enabling the
fabricated silicon nanowire FETs to serve as nonvolatile memory devices, although
they are far from being useful in their present state in these electronic testbed
structures. As shown in Figure 11.14a, the silicon nanowire has higher conduc-
tance, at the same gate voltage, during sweeping from 20V to
20V than the sweep
in the opposite direction. This is caused by the change in surface charge density
when applying a positive or negative gate bias. When applying a negative gate bias,
the surface negative traps were discharged; when applying a positive gate voltage,
the oxide traps were again charged. This makes the silicon nanowire-FET exhibit
two reversible conductance states as shown in Figure 11.14b. We measured the
memory performance of different devices and the results showed that the ratio of
ON/OFF states ranged from 3-10. We used relatively long (5 s) pulse times in the
write/erase operations in order to obtain the higher ON/OFF ranges from the
silicon nanowire-FETs. Shorter write/erase pulses resulted in two different con-
ductance states but with smaller ON/OFF ratios. For example, the ON/OFF ratio
of a silicon nanowire-FET memory device was
4 with the 5 s write/erase pulsing
B
but the ON/OFF ratio fell to
1.2 with 0.1 s write/erase pulsing. The shorter
pulsing times apparently led to an unfinished charging/discharging process.
B
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