MOLECULAR COMPUTING: INTEGRATION OF MOLECULES FOR NANOCOMPUTING - Bio-Inspired and Nanoscale Integrated Computing - page 317

Figure 11.11 shows the typical transfer characteristics of the devices under test
before and after the grafting of molecular monolayers. For compounds 1-3, the
drain current under the same gate bias decreased after the molecular grafting. The
amplitude of this decrease is in the order of 1

3. But I D increased slightly after
the grafting of 4. The hystereses observed in the I D -V g curves are very similar in
amplitude and shape before and after the molecular attachment (Fig. 11.11).
Therefore these hysteretic effects are caused by the device itself, not by the
molecular grafting.
The threshold voltage V T of the pseudo-MOSFET can be extracted based on
I D , which represents the onset of significant drain current (Fig. 11.12a). The V T
values shown in Figure 11.12a were determined from the V g axis intercept of the
I D,Sat 0.5 -V g characteristics linearly extrapolated [97-99]. We observed that the V T
became more negative (usually about 1

W 2 W

2 V) after grafting 1, 2 and 3 while less
negative for 4, relative to the control which was the Si-H surface before molecular
grafting. Though there are slight differences between the values of D V T when V T
was extracted from the forward and back scans (Fig. 11.12b) due to the inherent

B

V g (V)

20 10 0 − 10 − 20 20 10 0 − 10 − 20

− 0.04 1 2 − 0.04

− 0.03 − 0.03

0.02 − 0.02

−

− 0.01

− 0.01

0.00

0.00

− 0.04 − 0.04

3 4

− 0.03 − 0.03

− 0.02 − 0.02

− 0.01 − 0.01

0.00 0.00

20 10 0 − 10 − 20 20 10 0 − 10 − 20

V g (V)

Figure 11.11. Transfer characteristics of the devices under test before and after
the grafting of different molecular monolayers. The numbers (1, 2, 3, and 4) in
the illustrations correspond to the compounds 1-4, respectively. Data shown here
were collected under 5VofV D and is the average value for 14 devices from Row
0 on one chip, as described in Figure 11.10a, and they are characteristic of the
hystereses observed in all the devices. The gate bias was scanned first from +20 V
to 20V (forward) and then back from 20 V to +20V.