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The second approach is nanoimprinting lithography [67-69], which employs
molds fabricated using costly but fine methods, e.g., electron beam lithography or
the supperlattice nanowire pattern transfer (SNAP) method to be addressed
below. Williams and Heath demonstrated an array of 150 Silicon nanowires
with 15 nm wide at 34 nm pitch [68].
The third approach is the superlattice nanowire pattern transfer (SNAP)
method [48, 49]. Similar to the nanoimprinting, the SNAP method does not
separate nanowire growth and array formation clearly: Nanowires are formed at
the same time as they are aligned. In this method, a GaAs/AlGaAs superlattice is
first fabricated with molecular beam epitaxy (MBE). The AlGaAs of the super-
lattice is then etched to create parallel grooves between the GaAs layers. The
superlattice is then tilted in order to deposit metal onto the edges of the grooves,
forming metallic nanowires. The width of the metallic nanowires is defined by the
thickness of the GaAs layers in the superlattice; the pitch, or separation, between
the nanowires is defined by the thickness of the AlGaAs layers that are etched. The
nanowire array formed along the grooves is then transferred to a silicon wafer by
contacting the superlattice to an adhesive layer on top of the wafer. The metallic
nanowire array is released on the wafer by etching the GaAs oxide layer between
the nanowires and the GaAs layers. The metallic nanowires can be employed as
etch masks to form semiconductor nanowires on the wafer, e.g., silicon-on-SiO 2
wafer. Crossbar arrays can be formed by overlaying orthogonal arrays. Using this
method, Health's group has demonstrated a large-scale crossbar array, intended
as a high-density memory module [32]. The metallic nanowire array can also be
employed to fabricate molds for nanoimprinting [68], as discussed above.
Compared to the self-assembly approach, nanoimprinting and SNAP methods
are limited in the nanowires that can be employed, primarily due to the fact that
they form the nanowires and align them into arrays at the same time. Therefore, it
would be extremely hard to use them to fabricate arrays using nanowires with
heterostructures, such as the Ge/Si nanowires that were developed by Lieber [66].
However, compared to the self-assembly approach, nanoimprinting and the SNAP
method enjoy a greater control on the pitch and the position of the nanowires,
thereby producing much more uniform arrays.
11.3.2.2. Circuit and Architectural Solutions. Large-scale crossbar arrays
intended as memory units have been fabricated; small logic circuit based on
crossbar arrays have also been demonstrated. Inspired by these fabrications,
computer engineering researchers have proposed numerous architectural solutions
based on crossbar arrays. To achieve large scale integration, many have studied
the possibility of a hybrid circuit with both traditional CMOS transistors and
nanoscale crossbar arrays.
Lieber proposed a SWNT-based nonvolatile RAM device comprising
a series of crossed nanotubes wherein one parallel layer of nanotubes is
placed on a substrate and another layer of parallel nanotubes, orthogonal to
the first set, is suspended above the lower nanotubes by placing them on a
periodic array of supports [41]. The elasticity of the suspended nanotubes
 
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