MOLECULAR COMPUTING: INTEGRATION OF MOLECULES FOR NANOCOMPUTING - Bio-Inspired and Nanoscale Integrated Computing - page 301

and measured in nearly identical conditions [23] and it exhibited essentially linear
I(V) behavior within its noncrystalline temperature range.
Figure 11.3 shows the typical I(V) characteristics of an Au-(nitroaniline
OPE)-Au device at 60K [24, 25]. Positive bias corresponds to hole injection
from the chemisorbed thiol-Au contact and electron injection from the evaporated
contact. Unlike previous devices that also used molecules to form the active
region, this device exhibits a robust and large NDR with a valley-to-peak ratio
(PVR) of 1030:1 [24, 25]. We observed the NDR effect from the system up to
260K but not beyond. Since then, room temperature NDR has been seen in the
nanopores containing the SAM of the nitro OPEs [24].
Additionally, we demonstrated charge storage in a self-assembled nanoscale
molecular device that operated as a molecular dynamic random access memory
(mDRAM) with practical thresholds and output under ambient operation [25].
The memory device operates by the storage of a high or low conductivity state.
Because added electrons dramatically affect the conductivity of the molecular
system, the information state can be read by a conductivity check. Figure 11.4
shows the write, read, and erase sequence [25]. To further explore the mechanism
of this mNDR and mDRAM phenomenon, we have synthesized several related
compounds such as a nitroacetamide rather than a free nitroaniline moiety. After
testing in the nanopore, we found that nitroacetamide exhibited the NDR effect,
however, with a smaller PVR of 200:1 at 60K.
Figure 11.5 shows the measured input and output of an mDRAM cell using
the mononitro OPV in the nanopore at room temperature. To convert the stored
conductivity to standard voltage conventions, the output of the device was
Figure 11.2. (a) The starting substrate for the device fabrication is a 250 mm-thick
double side polished silicon wafer with 50 nm of low stress Si 3 N 4 . On the back
surface, the nitride was removed in a 400 mm by 400 mm square. The exposed silicon
was etched in an orientation-dependent anisotropic etchant through to the top
surface to leave a suspended (40 mmby40mm) silicon nitride membrane. Reed then
grew 100nm of SiO 2 thermally on the Si sidewalls to improve electrical insulation. A
single hole 30 to 50 nm in diameter was made through the membrane by electron
beam lithography and reactive ion etching (RIE). Because of the constrained
geometry, the RIE rates are substantially reduced so that the far side opening is
much smaller than the actual pattern, thereby rendering the cross section bowl-
shaped geometry. (b) and (c) A gold contact of 200nm thickness was evaporated
onto the topside of the membrane, filling the pore with Au. The sample was then
immediately transferred into a solution to self-assemble the active electronic
component, illustrated here with an unfunctionalized sulfur-tipped OPE. The sample
was then rinsed, quickly loaded into a vacuum chamber, and mounted onto a liquid
nitrogen cooling stage for the bottom Au electrode evaporation, where 200nm Au
was evaporated at 77K at a rate of less than 1 ˚ /s. The devices were then diced into
individual chips, bonded onto packaging sockets and loaded into a variable
temperature cryostat and measured with a Semiconductor Parameter Analyzer.