FAULT- AND DEFECT-TOLERANT ARCHITECTURES FOR NANOCOMPUTING - Bio-Inspired and Nanoscale Integrated Computing - page 283

composed of 10 12 devices to compare their fault mitigation potential. It was shown
that a NANDMUX based architecture on such a chip could be reliable 90% of the
time if the devices had a failure probability 0.01, however, the R required to

r

10 6 .
Reference [28] provides a comparative study of the von Neumann NAND and
MAJ MUX architectures. These comparisons have been made in the presence of
(i) only noisy gates and (ii) noisy gates and interconnects, for different values of R.
Some of the results are discussed below. The first five results are obtained in the
presence of only noisy gates while the rest of them are determined in the presence
of both noisy gates and interconnects.

achieve this was

E

For large gate failure probabilities, the performance of the MAJ MUX
architecture is substantially better than the NAND MUX system.
As the gate failure probability increases beyond a certain threshold, increas-
ing N degrades the performance of the NAND MUX system. But for MAJ
MUX, increasing N results in marginal improvement of performance.
For small gate failure probabilities, the performance of the MAJ MUX
architecture is better than NAND MUX at lower R. But both MUX
architectures tend to reach similar steady state reliability values at higher R.
For small gate failure probabilities, the increase in N results in a higher
probability of malfunction. This is because the chance of error introduction
due to more noisy gates may be counterproductive [57]. Hence a higher R is
required to improve the performance of the architecture. This is true for
both MUX schemes.
The individual device failure probabilities that can be tolerated by incor-
porating a MAJ MUX scheme with 50 R 100 on a chip are determined

r r

and compared to theoretical results.
MAJ MUX has a higher reliability than NAND MUX in the presence of
small and large noise spikes at the inputs and interconnects.
In the presence of signal noise at the inputs and interconnects, a MUX
system with a large bundle size N must have higher R to provide better
reliability than a MUX system with small N.

10.4.2. Probabilistic Transfer Matrices (PTMs)
PTMs have been used in [61] to model defective logic gates using matrix
representations, an idea that dates back to [62]. The PTM for a NAND gate
with a failure probability of e is given by

2 3

e

1 e

4 5 ;

e 1 e

PTM NAND ¼ ð 10 : 1 Þ

e 1 e

1 e e