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Defect prone
reconfigurable
nanofabric
System tolerant
to transient
errors
Structural
redundancy
Non-mission
critical systems
Computationally
less expensive and
time-consuming
Design
System tolerant
to both
permanent and
transient errors
Defect mapped
reconfigurable
nanofabric
Mission critical
systems
Structural
redundancy
Figure 10.8. Application of our methodology.
its operational environment, hence, determining these parameters is experimental.
The toolset is used to determine whether these parameters provide the necessary
reliability without causing unacceptable delay, area and cost penalties.
10.4. RELIABILITY EVALUATION OF DEFECT/FAULT-TOLERANT
NANOCOMPUTING
As discussed earlier, due to increased defects in nanoscale devices, designing
reliable digital circuits with such devices is a major challenge. Development of
accurate reliability estimation methodologies is critical in analyzing the robustness
of circuits designed from unreliable nanoscale devices.
Recently, a number of methodologies have been developed to evaluate circuit
reliability, methodologies that analyze the reliability independent of the technol-
ogy used to fabricate nanoscale devices. Methodologies based on probabilistic
model checking (PMC) have been developed to evaluate circuit architecture
reliability and demonstrated its applicability at the logic gate and logic block
levels. [30, 31] developed matrix-based gate-level models called probabilistic
transfer matrices (PTM) that are used for circuit reliability analysis. Concurrently,
but independently [32], proposed a technique to develop probabilistic models
called probabilistic gate models (PGM) for unreliable logic gates and used these
models to analyze the circuit reliability.
10.4.1. Probabilistic Model Checking (PMC)
PMC is an algorithmic procedure for ascertaining whether a given probabilistic
system satisfies probabilistic specifications such as the probability of logical
correctness at the output of a logic network must be at least 90% given that each
 
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