FAULT- AND DEFECT-TOLERANT ARCHITECTURES FOR NANOCOMPUTING - Bio-Inspired and Nanoscale Integrated Computing - page 275

redundancy insertion methodology maps the non-redundant or redundant covers
of the systems onto the structurally redundant nanofabrics by generating pseudo-
random maps.
These pseudo-random maps (i) avoid defective components if and only if a
defect map is available for the nanofabric, since a designer can opt not to generate
a defect map, (ii) introduce redundant structural units at the different hierarchies
of the nanofabrics, and (iii) attempt to reduce routing latencies while inserting
structural redundancy. As part of this work, scripts are developed that use these
maps to hierarchically translate each primitive flow of the covers onto the
structurally redundant nanofabric models. The stress is on hierarchy, since the
computational time required for steady state probability analysis of hierarchically
mapped designs is less as compared to flat models [28]. Such a specific behavioral-
structural mapping of a design is called a cover-map.

10.3.2.4. Design Flow. Figure 10.7 shows the design flow of the proposed
design and analysis methodology. Below, the different steps are outlined in detail.

1. Test circuits are run physically on the nanofabric to compute the
approximate junction defect rate. A model of the specific molecular

Molecular
nanofabric

1. Build model
in SMART

Probability of each
PE being reachable

Broadcast mechanism

3. Analyze broadcast
coverage and network
connectivity

2. Probabilisitic
defect map

Hierarchical
mapping

4. Inject signal
noise on
interconnects

5. Translate systems
onto nanofabric

7. Granularity-
based
redundancy
insertion

No

6. Meets
specification?

Reliability, area,
cost, delay

Generate
configuration bits

Ye s

Figure 10.7. Design Flow.