FAULT- AND DEFECT-TOLERANT ARCHITECTURES FOR NANOCOMPUTING - Bio-Inspired and Nanoscale Integrated Computing - page 274

Flow 0

Flow 1 Flow 2

Flow 0

Flow 2

Flow 1

Figure 10.5. Cover for AR filter design.

A0 A1 B1

B0

PE PE PE

A B

B2

Node 1 is
triplicated

A2 PE Region

1 Voter

Voter

TMR at the PE level

2

Flow 3

TMR at the region level

4

3

2

Flow 5

3 4

Flow 2

Mapping unit

(a)

Voter

TMR at the MU level

(b)

Figure 10.6. Behavioral and structural redundancy.