FAULT- AND DEFECT-TOLERANT ARCHITECTURES FOR NANOCOMPUTING - Bio-Inspired and Nanoscale Integrated Computing - page 271

Via1 Via2

Vi a 5

Via4

Via3

20x10 Grid

Figure 10.4. Molecular Nanofabric.

current model is used to represent the fault classes that have the highest
probability of occurrence in chemical self-assembly fabrication processes.

10.3.2. Methodology
The instance-based methodology proposed in [23-25] can be used to design and
analyze molecular logic systems. The methodology entails (i) developing a script
to translate specifications of molecular nanofabric instances in terms of number of
PEs, size of crossbar for each PE, etc. into probabilistic transition models,
(ii) determining the exact failure probability of each junction by running test
circuits physically on the nanofabrics and using these values on the nanofabric
models to generate probabilistic defect maps, (iii) developing a script to insert
behavioral redundancy in the designs and/or structural redundancy at the
different structural hierarchies of the nanofabrics and (iv) developing Markovian
and state space traversal techniques to analyze redundant instances of different
designs that are mapped onto the nanofabrics.
Many specific design instances have to be analyzed by this methodology to
predict general performance trends of general structurally redundant architec-
tures, a drawback that is common for instance-based methodologies. This issue is
addressed by hierarchical modeling and state space partitioning techniques
discussed later in this section.

10.3.2.1. Test Circuits. The probabilistic defect mapping technique is based
on limited on-line testing of nanofabrics. Simple test circuits are configured on the
nanofabrics to get a notion of the probability of the crossbar-based PEs being