FAULT- AND DEFECT-TOLERANT ARCHITECTURES FOR NANOCOMPUTING - Bio-Inspired and Nanoscale Integrated Computing - page 270

While such reconfigurable architectures may aid in circumventing manufac-
turing defects at the nanoscale, they will not provide tolerance to natural external
transient faults. The addition of structural redundancy a priori may enhance the
reliability of such systems in the presence of transient faults.
There are two general classes of defect mapping and avoidance techniques:
(i) techniques that use test circuits to find the location and number of defects on a
reconfigurable nanofabric [19, 21], and (ii) broadcast-based methods that flood
test packets through the whole nanofabric to locate nonreachable nodes [22]. The
test circuits or packets placed on the fabric during the self-diagnosis phase utilize
resources that are available later for normal logic mapping. Although such defect
mapping techniques can be performed with massive parallelism, they have been
reported to be expensive in terms of cost and time.
In [23-25], a defect-mapping and hierarchical redundancy insertion metho-
dology is presented which is discussed below in detail. First, we present the target
nanofabric and fault models for this methodology followed by the details of the
methodology and a proposed automation framework.
10.3.1. Nanofabric and Fault Models
10.3.1.1. Nanofabric Model. The target nanofabric model is composed of
processing elements (PEs) built from crossbars. Figure 10.4 shows a nanofabric
composed of a grid of PEs connected together. This model is a combination of the
nanofabric models used in [22] and [26]. The PEs are modeled to function as
simple single-bit arithmetic logic units (ALUs), 8-bit adders or 8-bit combina-
tional multipliers depending on the application being targeted. In this model, each
PE has 4 transceivers that are connected to the 4 asynchronous bidirectional
interconnects. Figure 10.4 also shows vias that are used to interface the nanofabric
with external circuitry. The nanofabric model has three levels of hierarchy:
regions, mapping units (MUs) and components (defect-mapping technique
discussed in [22] uses a monolithic model).
10.3.1.2. Fault Model. The fault model considers the effects of both
manufacturing defects and transient faults. Since the proposed work focuses on
crossbar-based nanofabrics, the faults relevant to such nanofabrics are discussed.
The manufacturing defects in the crossbar cause stuck-open and stuck-closed
faults at the junctions and wires. Since the yield of the crossbar is very low in the
presence of stuck-closed faults, it is possible to bias the chemical self-assembly
process to decrease the probability of such faults [19]. Hence, only stuck-open
faults at the junctions and wires are considered.
The methodology [23-25] models these faults as the probability of failure to
program the molecular diodes or latches to the appropriate logic value. Also, the
faults at the interconnects are modeled as Gaussian failure distributions that
quantify the effect of signal noise. It is also assumed that the faults at the junctions
and interconnects are independent, identical and uniformly distributed (i.i.u). This
fault model can be changed in the proposed toolset discussed below and the