FAULT- AND DEFECT-TOLERANT ARCHITECTURES FOR NANOCOMPUTING - Bio-Inspired and Nanoscale Integrated Computing - page 269

10.2.2.2. Cyclic Redundancy Check (CRC). The CRC is a very powerful
and easily implemented technique to obtain data reliability. CRC is a type of hash
function used to produce a checksum, a small fixed number of bits against a block
of data. The checksum holds redundant information about the block of data that
helps the recipient detect errors. A CRC is computed and appended before
transmission or storage, and verified afterwards by the recipient to confirm that no
changes occurred during transmission. It is one of the most widely used techniques
for error detection in data communications. The technique is popular because
CRCs have extreme error detection capabilities, have little overhead and are easy
to implement. Moreover, they are simple to implement in binary hardware and are
easy to analyze mathematically. Even parity is actually a special case of a CRC,
where the 1-bit CRC is generated by the polynomial x+1.
10.2.2.3. Error-Correcting Code (ECC). An error-correcting code is an
algorithm for expressing a data signal such that any errors which are introduced
can be detected and corrected, within certain limitations, based on the other parts
of the signal. In an ECC, each data signal conforms to specific rules of
construction so that departures from this construction in the received signal can
generally be automatically detected and corrected. It is used in computer data
storage and transmission. The simplest error-correcting codes can correct single-
bit errors and detect double-bit errors. There are other codes which can detect or
correct multi-bit errors. Some of the examples of ECC are Hamming code, BCH
code, Reed-Muller code, Binary Golay code, and convolutional code. ECC-based
computer memory provides greater data accuracy and system uptime by protect-
ing against soft errors.
10.3. DEFECT TOLERANCE THROUGH RECONFIGURATION
Chemically self-assembled molecular nanofabrics are by nature very regular and
homogeneous, hence, well-suited for reconfigurability [17-19]. It is reported that
the reconfiguration is the most effective technique to cope with manufacturing
defects in nanodevices. Reconfigurable fabrics are composed of programmable
logic elements [like configurable logic blocks (CLBs)] and interconnects which can
be configured to implement any logic circuit. It is expected that reconfigurable
fabrics made from next generation fabrication processes will go through a post-
fabrication defect mapping phase during which these fabrics are configured for
self-diagnosis [20, 21]. Thus, defect tolerance in such fabrics can be achieved by
detecting faulty components during an initial defect map phase and excluding
them during actual configuration. In other words, design of reliable digital logic
and architectures on unreliable nanofabrics will require defect mapping followed
by defect avoidance to circumvent hard faults. Defect mapping is the process of
finding defect locations in a nanofabric, and defect avoidance is the process of
mapping a computing logic on a faulty nanofabric knowing its defect-maps.