FAULT- AND DEFECT-TOLERANT ARCHITECTURES FOR NANOCOMPUTING - Bio-Inspired and Nanoscale Integrated Computing - page 263

10
FAULT- AND DEFECT-TOLERANT
ARCHITECTURES FOR
NANOCOMPUTING
Sumit Ahuja, Gaurav Singh, Debayan Bhaduri,
and Sandeep Shukla
In the recent past, CMOS manufacturing technology has been successfully
downscaled to create feature sizes below 100 nm; it is predicted to reach the
22 nm mark very soon. But with the predicted demise of Moore's law, continued
success of the electronic industry will increasingly depend on emerging nano-
technologies. These emerging nanotechnologies have influenced the rapid devel-
opment of nonsilicon nanodevices such as carbon nanotubes and molecular
switches. CMOS or not, affordable manufacturing of defect-free nanosystems
seems unlikely. Besides manufacturing defects, various transient faults will affect
these systems. Therefore, there is a need for developing computing architectures
that are tolerant to defects and faults and that may be one of the ways to avoid an
industrial meltdown. This chapter provides a survey of techniques and architec-
tures for providing defect- and fault-tolerance to nanocomputing.
10.1. INTRODUCTION
10.1.1. The Micro to Nano Trend
For four decades, the rapid pace of improvement in microelectronics has been
based on the ability to decrease the minimum feature sizes used to fabricate
integrated circuits. The different parameters associated with integrated circuits
that have improved due to such feature scaling are outlined in Table 10.1. One of
the improvements that is frequently cited is the improvement in integration level;
this is expressed as Moore's law—the number of components per chip doubles
every 24 months.