NANOSCALE STANDARD DIGITAL MODULES - Bio-Inspired and Nanoscale Integrated Computing - page 260

TABLE 9 . 13 . Frequency Assignments in the Programmable
Priority Encoder Implementation
Node Sending frequency Receiving frequency

Binary p inputs f adc -

Input nodes (step 1) - f adc

Output node (step 1) - f adc

Input nodes (step 2) Variable (f i ) -

Output node i (step 2) - f i

the highest priority node reach the output node. Note that this index is the index
of the highest priority node when the data has been shifted p times. Therefore, as
the last step, the output node finds [(received index-p) mod N] as the final output
of the programmable priority encoder. Table 9.13 shows the frequency assign-
ments for implementing a spin-wave programmable priority encoder.
The programmable priority encoder can be used to determine which interrupt
request should be handled in the case that the priority order of the interrupts is not
fixed. For instance, a programmable priority encoder can be used in designing a
''fair'' system. In a fair system, whenever an interrupt request is handled, its
priority becomes the lowest priority for the next interrupt handling cycle. By using
a programmable priority encoder the winning interrupt node will determine the
next priority order.

9.5. CONCLUSIONS

In this chapter, we presented a set of nanoscale, standard combinational modules
by exploiting the computing features of spin waves. We showed that a number of
these widely used, standard arithmetic and logic digital modules including full
adders, multipliers, decoders, encoders, multiplexers, and demultiplexers can be
implemented by employing the concurrent write feature and superposition
property of the spin waves. In addition, we demonstrated how to implement
more complex modules such as priority encoders and shifters by using spin-wave
switches. The universality of these modules ensures the possibility of realizing any
logic switching functions. Sequential systems can be implemented by adding
latches to the combinational circuit. The latches or D flip-flops can be easily
simulated by the processing nodes. One possible extension of this research could
the investigation of how nanoscale latches can be implemented using the
nanoscale memory technology.

REFERENCES

1. M. Ercegovac, T. Lang, and J. Moreno. Introduction to Digital Systems. New York:
Wiley, 1999.