NANOSCALE STANDARD DIGITAL MODULES - Bio-Inspired and Nanoscale Integrated Computing - page 247

TABLE 9 . 1 . Frequency Assignments in the Multiplier Implementation
Node Sending frequency Receiving frequency

Binary x input nodes (step 1) f adc -

Intermediate nodes t (step 1) - f adc

Binary y input nodes (step 2) f adc -

Intermediate nodes t (step 2) - f adc

Intermediate nodes t (step 3) f out -

Output node (step 3) - f out

The output node's receiving frequency is tuned on the t nodes' sending
frequency, so that it receives the superposition of these waves. In this fashion,
x number of y is accumulated to generate the multiplication operation. Note
that 2 k nodes are required as t since maximum value of x is 2 k .

Table 9.1 shows the frequency assignments for implementing a spin-wave
multiplier.

9.3. NANOSCALE SPIN-WAVE STANDARD LOGIC

In this section we demonstrate how standard combinational logic modules can be
implemented at the nanoscale. We employ parallel features of spin waves for
implementing these logic modules: logic gates, decoders, encoders, multiplexers,
and demultiplexers.

9.3.1. Logic Gates
The utilization of spin waves provides an opportunity to perform different logic
functions in one device controlling the initial phases of spin waves and the voltage
threshold to which the output voltage is compared. As explained in Chapter 7,
Khitun and Wang showed how the two-bit gates, AND, OR, and the one-bit NOT
can be implemented on the simple spin-wave prototype device [5, 6]. In this section
we first briefly explain how they have implemented these logic gates, and next, we
show how to extend their design to implement other logic functions such as
NAND, NOR, XOR, and XNOR.
As explained in Chapter 7, the input information is coded into the polarity of
the voltage pulse applied to the input ACPS lines and is detected at the output
port [5]. The output logic state is determined by comparing the detected voltage to
a reference voltage, V ref . Assume that the measured inductive voltage produced by
a single spin wave at the output port is V 1 . The reference voltage V ref can be a
function of V 1 as shown below. The measurement is performed at the moment two
spin wave packets arrive at the detecting ACPS line t m . The exact choice of t m
depends on the logic function one needs to realize.