PARALLEL COMPUTING WITH SPIN WAVES - Bio-Inspired and Nanoscale Integrated Computing - page 240

and allow for concurrent read/write operations. Exploiting such parallel features,
a set of generic and fast parallel processing techniques were introduced.
REFERENCES
1. M. M. Eshaghian-Wilner and S. Navab. Generic parallel processing techniques for
nanoscale spin-wave architectures. 2007 World Congress in Computer Science,
Computer Engineering, and Applied Computing WORLDCOMP'07. In: Proceedings
of the 2007 International Conference on Parallel and Distributed Processing Techni-
ques and Applications (PDPTA'07): pp 221-227.
2. M. M. Eshaghian-Wilner and S. Navab. Efficient parallel processing with spin-wave
nanoarchitectures. Journal of Supercomputing; October 2008.
3. M. M. Eshaghian-Wilner, S. Navab, A. Khitun, and K. L. Wang. The Spin-wave
Reconfigurable Mesh and Labeling Problem. ACM Journal on Emerging Technologies
in Computing Systems, 3(2, no. 5): July 2007.
4. M. M. Eshaghian-Wilner, A. Khitun, S. Navab, and K. L. Wang. A nanoscale
architecture for constant time image processing. Physica Status Solidi A, 204(6):
pp 1931-1936, June 2007.
5. M. M. Eshaghian-Wilner, L. Lau, S. Navab, and D. Shen. Parallel graph formations of
partial-order multiple-sequence alignments using nano-, micro-, and multi-scale re-
configurable meshes. Submitted to IEEE Transactions on NanoBioScience: 2008.
6. A. V. Oppenheim, R. W. Schafer, and J. R. Buck. Discrete-Time Signal Processing.
Upper Saddle River, NJ: Prentice Hall, 1999.
7. http://www.bores.com/courses/intro/filters/4_fir.htm.
8. http://www.freqdev.com/guide/DgtlFltrDsgnGd.pdf.
9. M. M. Eshaghian-Wilner and S. Navab. Parallel and fault-tolerant routing in the
nanoscale spin-wave architectures. 2007 World Congress in Computer Science,
Computer Engineering, and Applied Computing WORLDCOMP'07. In: Proceedings
of the 2007 International Conference on Computer Design (CDES'07): pp 3-9.
10. C. Constantinescu. Trends and challenges in VLSI circuit reliability. IEEE Microwaves,
23: pp. 14-19, Jul-Aug 2003.
11. S. Roy and V. Beiu. Majority multiplexing—Economical redundant fault-tolerant design
for nano architectures. IEEE Transactions on Nanotechnology, 4(4): pp 441-451, Jul 2005.
12. D. Bhaduri, S. K. Shukla, and Nanoprism. A tool for evaluating granularity vs.
reliability trade-offs in nano architectures. GLSVLSI, ACM, Boston, Apr 2004.
13. S. K. Shukla, G. Norman, D. Parker, and M. Kwiatkowska. Evaluating the reliability
of defect-tolerant architectures for nanotechnology with probabilistic model checking.
Proceedings of the International Conference on VLSI Design 2004.
14. P. T. Gauehan, B. V. Dao, S. Yalamanchili, and D. E. Schimmet. Distributed,
deadlock-free routing in faulty, pipelined direct interconnection networks. IEEE
Transactions on Computers, 6: pp 651-665, 1996.
15. B. Almohammand and B. Bose. Fault-tolerant communication algorithms in
toroidal networks. IEEE Transactions on Parallel and Distributed Systems, 10: pp
976-983, 1999.