SPIN-WAVE ARCHITECTURES - Bio-Inspired and Nanoscale Integrated Computing - page 222

dc resistance. In our calculation, we neglected the additional losses due to the ACPS
line resistance. In Figure 7.18, we present the results of numerical simulations
showing the inductive voltage as a function of time obtained in two cases: Spin-
wave packets are excited in phase (the solid line) and out of phase (the dashed line).
The results of simulations illustrate the output of the prototype logic device
described above. As shown in Figure 7.18, the amplitude of the inductive voltage
is maximum when the spin-wave packets are coming in phase. In the other case,
the waves from two packets compensate each other and produce inductive voltage
of much less amplitude.
7.10. CONCLUSIONS
In this chapter, three nanoscale architectures were presented: the reconfigurable
mesh, crossbar, and fully interconnected cluster. In these architectures, both
communication and computation are performed using spin waves. Furthermore,
computation is done in both analog and digital modes. A hierarchical multiscale
architecture was also presented that is an efficient integration of the spin-wave
modules within a MEMS architecture.
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