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inductive voltage produced by a single spin wave. As we will show below, it is
possible to realize different logic gates AND, OR, and NOT controlling the
relative phase of the spin waves.
7.7.2. Logic Functionality
The utilization of spin waves provides an opportunity to perform different logic
operations in a single device by controlling the initial phases of spin waves. The set
of logic gates, i.e., the two-bit gates, AND, OR, and the one-bit NOT gate can be
demonstrated on the prototype three-terminal device as shown in Figure 7.13. The
edge ACPS lines are considered as the input terminals, and the ACPS line shown
in the middle is the output port. The input information is coded into the polarity
of the voltage pulse applied to the edge ACPS lines (for example, V input =+10 V
corresponds to the logic state 1
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, and V input = 10 V corresponds to the logic
state 0
). We assume the input terminals are placed equidistantly from the output
one. In order to detect the output signal V ind we use the time-resolved inductive
voltage measurement. To recognize the output logic state we introduce a reference
voltage V ref . We assign the output logic state 1
W
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otherwise. The measurement is performed at the moment of spin-wave packet
arrival to the detecting ACPS line, t m . The exact choice of t m depends on the logic
function one needs to realize.
The one-bit NOT gate (inverter) can be obtained measuring the inductive
voltage produced by spin waves excited by one of the input lines. Taking t m =
p g/v ph (where g is the distance between the contacts and v ph is the spin-wave phase
velocity), and V ref =0 V, we achieve the required logic correlation. Next, the two-
bit AND gate can be realized when t m =2 p g/v ph , and V ref =0.5mV. Two spin-
wave packets coming in phase enhance the amplitude of the produced inductive
voltage, and cancel each other when coming out of phase. The nonzero reference
voltage is needed to avoid the effect caused by the finite size of the detecting ACPS
line. The OR gate can be realized by analogy, taking t m =2 p g/v ph , and V ref =
0.5mV. In Table 7.1, we have summarized the input/output correlations into the
truth tables for different logic gates.
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if V ind W
V ref , and logic state 0
TABLE 7 . 1 . Truth Tables for AND and OR Gates
AND
OR
V ref =0.5mV
V ref = 0.5mV
Input
voltage
Logic
state
Output
voltage
Logic
state
Input voltage
Logic
state
Output
voltage
Logic
state
+1 V +1 V 1
1 +27mV 1
+1 V +1 V 1
1 +27mV 1
+1 V
1 V 1
0
0mV
0
+1 V
1V 1
0
0mV
1
1 V +1 V 0
1
0mV
0
1 V +1 V 0
1
0mV
1
1V
1V 0
0
27mV
0
1V
1V 0
0
27mV
0 o
 
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