Information Technology Reference
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Figure
7.8.
Reconfigurable spin-wave switch possible connections.
a significant improvement considering the
O
(log N) lower-bound on the time delay
for implementing such networks in VLSI using traditional electrical interconnects.
Another key advantage is that the spin-wave fully interconnected network can be
laid out in O(N
2
) area as opposed to O(N
4
). Of course, the unit of area is in order
of nanometer as opposed to the standard micron technology. In this architecture,
information is encoded into the phase of spin waves, and no charge is transmitted.
As a result of this, power consumption can be significantly reduced in this
architecture (compared to other nanoscale architectures).
Figure 7.9 shows the top view of the architecture in which the N computing
nodes are placed around a circle on a magnetic film. Each node is an asymmetric
coplanar strip (ACPS) line (described later in Section 7.7), which can be used as a
sender or receiver at each point of time. Figure 7.10 shows the cross view of the
layout of this architecture on a semiconductor chip. The area requirement of this
architecture is O(N
2
), as opposed to the O(N
4
) area requirement if electrical
interconnects were to be used. We should also note that in this architecture all the
distances are in nanoscale. Also unlike the network with electrical interconnections,
A
L
B
K
C
J
D
I
E
F
H
G
Figure
7.9.
The top view of the architecture with full spin-wave interconnectivity.
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