Information Technology Reference
In-Depth Information
circulating memory storage is not a new concept and can be traced back to at least
the mercury delay lines that were used to implement storage in the commercial
tube computers of the 1950s.
4.11.5. 4-bit Processor
A simple 4-bit processor, designed using QCADesigner, has been reported in [76].
This processor was designed mainly as a proof-of-concept to demonstrate that
reasonably complex architectures are possible to build using QCA technology, as
well as to create a platform for investigating the inherent zone level pipelining.
This circuit is intended to demonstrate the level of complexity that can be handled
by QCADesigner, not as a demonstration of the ideal architecture for computing
using QCA technology. Such architectures are still being developed.
The processor is limited to operate on instructions fed into the circuit directly
at the inputs; no program memory is used. The design incorporates a 4 4
random access memory (RAM) to provide temporary storage. The design is based
on a simple accumulator architecture shown in Figure 4.30.
Basic arithmetic and logic operations are implemented in the arithmetic logic
unit (ALU). This ALU is built by extending the 4-bit adder. The ALU layout can
be seen in Figure 4.31.
An input to the ALU requires 11 clock cycles (44 consecutive clock zones) to
propagate through the entire unit. Due to the natural pipelining introduced by the
clocking, a new input can be applied to the ALU in each consecutive clock cycle,
allowing 11 operations to be in the pipeline at any one time.
4
0
4
1
Ins [8-5]
B
A
ALU
Dataout
Ins [4]
4x4-bit
memory
4
4
Ins [9]
R/W
ALUOp (Ins [3-1])
Accumulator
Ins [8-7]
Address
Datain
Acc
10
Instruction [9-0]
4
Figure 4.30. Processor architecture.
 
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