COMPUTING WITH QUANTUMDOT CELLULAR AUTOMATA - Bio-Inspired and Nanoscale Integrated Computing - page 129

technology. As a result, one of the main objectives of this effort is to provide
motivation for further research into the implementation of such devices and
development of a continued dialog between circuit designers and researchers
investigating these implementations.

4.11. EXAMPLE CIRCUIT DESIGNS

The following sections describe a relatively small subset of the many circuit
designs that have been already been reported in the literature. The design and
layout of these example circuits has been done manually. Early work on the
automatic placement and routing of QCA circuits has also been reported [69-71],
as well as early work on minimizing the overall hardware requirements through
majority minimization techniques [60, 72, 73].

4.11.1. QCA Addition
Of the variety of information processing tasks that computers perform, the most
basic is certainly the addition of two single digit binary numbers. References
[56, 74] investigate the design and layout of a QCA full adder, using QCADesigner,
in more detail. The schematic and layout for the full adder are shown in Figure 4.18.
It should be noted that these layouts represent a snapshot of the circuit in operation,
which is why only one of the clocking phases has cells that are latched.
The apparent underutilization of space in this layout is a result of design
requirements that attempt to minimize the crosstalk between different parts of the
QCA circuit. The simulation results for this adder are shown in Figure 4.19. The
delay between the application of the input and the appearance of the associated
output is due to the inherent delay in the circuit. Figure 4.18 shows the four
clocking zones (1 clock cycle) between the input and output.
A QCA ripple-carry adder is implemented by cascading n 1-bit QCA full
adders. The schematic for a 4-bit adder is shown in Figure 4.20. As the inputs

D1 D2

M D1 D2 M D3

Sum

Sum

D1 D2 D3

M Carry

Carry

D0 D0 D0

Cin A B

Cin A B

Figure 4.18. Schematic and layout of a majority-based full adder.