Glossary - The HCS12/9S12: An Introduction to Software and Hardware Interfacing - page 836

Refresh An operation performed on dynamic memories in order to retain the stored
information during normal operation.
Refresh period The time interval within which each location of a DRAM chip must be
refreshed at least once in order to retain its stored information.
Register A storage location in the CPU. It is used to hold data and/or a memory address
during the execution of an instruction.
Relative mode An addressing mode that uses an 8- or 16-bit value to specify the branch
distance for branch instructions. If the sign of the value is negative, then the branch is a
backward branch. Otherwise, the branch is a forward branch.
Remote frame A frame sent out by a CAN node to request another node to send data

frames.
Repeated start condition This condition is used in the I 2 C protocol. A repeated start signal
is a start signal generated without first generating a stop signal to terminate the current
communication. This condition is used to change the direction of data transfer or change
the partner of data communication.
Reset A signal or operation that sets the flip-flops and registers of a chip or microprocessor
to some predefined values or states so that the circuit or microprocessor can start from a
known state.
Reset handling routine The routine that will be executed when the microcontroller or
microprocessor gets out of the reset state.
Reset state The state in which the voltage level of RESET the pin of the HCS12 is low. In
this state, a default value is established for most on-chip registers, including the program
counter. The operation mode is established when the HCS12 exits the reset state.
Resynchronization All CAN nodes perform resynchronization within a frame whenever a
change of bit value from recessive to dominant occurs outside of the expected sync_seg
segment after the hard synchronization.
Resynchronization jump width The amount of lengthening in phase_seg1 or shortening
in phase_seg2 in order to achieve resynchronization in every bit within a frame. The
resynchronization jump width is programmable to between 1 and 4.
Return address The address of the instruction that immediately follows the subroutine call
instruction (either JSR or BSR).
Rise time The amount of time a digital signal takes to go from logic low to logic high.
ROM (read-only memory) A type of memory that is nonvolatile in the sense that when power
is removed from ROM and then reapplied, the original data are still there. ROM data can
only be read—not written—during normal computer operation.
Row address strobe (RAS) The signal used by DRAM chips to indicate that row address logic
levels are applied to the address input pins.
RS232 An interface standard recommended for interfacing between a computer and a modem.
This standard was established by EIA in 1960 and has since been revised several times.
Serial Peripheral Interface (SPI) A protocol proposed by Freescale that uses three wires to
perform data communication between a master device and a slave device.
Seven-bit addressing In the I 2 C protocol, the master device may use a 7-bit value to specify
the device for communication.
Signal conditioning circuit A circuit added to the output of a transducer to scale and shift the
voltage output from the transducer to a range that can take advantage of the whole dynamic
range of the A/D converter being used.