Glossary - The HCS12/9S12: An Introduction to Software and Hardware Interfacing - page 832

Extended mode An addressing mode that uses a 16-bit value to represent the address of a
memory location.
Fall time The amount of time a digital signal takes to go from logic high to logic low.
Floating signal An undriven signal.
Foreground receive buffer The CAN receive buffer that is accessible to the programmer.
Form error An error detected when a fixed-form bit field contains one or more illegal bits in
the CAN bus protocol.
Frame pointer A pointer used to facilitate access to parameters in a stack frame.
Framing error A data communication error in which a received character is not properly
framed by the start and stop bits.
Full-duplex link A communication link that allows both transmission and reception to
proceed simultaneously.
General call address A special value (all 0s) used by the master to address every device
connected to the I 2 C bus.
Global memory Memory that is available to all programs in a computer system.
Half duplex link A communication link that can be used for either transmission or reception,
but only in one direction at a time.
Hard synchronization The synchronization performed by all CAN nodes at the beginning of

a frame.
Hardware breakpoint A hardware circuit that compares address and data values to predetermined
data in setup registers. A successful comparison places the CPU in background debug mode or
initiates a software interrupt (SWI).
Identifier acceptance filter A group of registers that can be programmed to be compared with
the identifier bits of the incoming frames to make an acceptance decision.
Idle A continuous logic high on the RxD line for one complete character time.
Illegal opcode A binary bit pattern of the opcode byte for which an operation is not defined.
Immediate mode An addressing mode that will be used as the operand of the instruction.
Indexable data structure A data structure in which each element is associated with an
integer that can be used to access it. Arrays and matrices are examples of indexable data
structures.
Indexed addressing mode An addressing mode that uses the sum of the contents of an
index register and a value contained in the instruction to specify the address of a memory
location. The value to be added to the index register can be a 5-, 9-, or 16-bit signed value.
The contents of an accumulator (A, B, or D) can also be used as the value to be added to the
index register to compute the address.
Inline assembly instruction Assembly instructions that are embedded in a high-level

language program.
Input capture The HCS12 function that captures the value of the 16-bit free-running main
timer into a latch when the falling or rising edge of the signal connected to the input-capture
pin arrives.
Input handshake A protocol that uses two handshake signals to make sure that the peripheral
chip receives data correctly from the input device.
Input port The part of the microcontroller that consists of input pins, the input data register,
and other control circuitry to perform the input function.