Instruction Set Reference - The HCS12/9S12: An Introduction to Software and Hardware Interfacing - page 826

UnimplementedISR, // CAN0 receive

UnimplementedISR, // CAN0 errors

UnimplementedISR, // CAN0 wake-up

UnimplementedISR, // flash

UnimplementedISR, // EEPROM

UnimplementedISR, // reserved

UnimplementedISR, // reserved

UnimplementedISR, // IIC bus

UnimplementedISR, // BDLC

UnimplementedISR, // CRG self clock mode

UnimplementedISR, // CRG PLL clock

UnimplementedISR, // pulse accumulator B overflow

UnimplementedISR, // modulus down counter underflow

UnimplementedISR, // portH

UnimplementedISR, // portJ

UnimplementedISR, // ATD1

UnimplementedISR, // ATD0

UnimplementedISR, // SCI1

UnimplementedISR, // SCI0

UnimplementedISR, // SPI0

UnimplementedISR, // pulse accumulator input edge

UnimplementedISR, // pulse accumulator A overflow

UnimplementedISR, // enhanced capture timer overflow

UnimplementedISR, // enhanced capture timer Ch7

UnimplementedISR, // enhanced capture timer Ch6

UnimplementedISR, // enhanced capture timer Ch5

UnimplementedISR, // enhanced capture timer Ch4

UnimplementedISR, // enhanced capture timer Ch3

UnimplementedISR, // enhanced capture timer Ch2

UnimplementedISR, // enhanced capture timer Ch1

UnimplementedISR, // enhanced capture timer Ch0

rtiISR, // real time interrupt

IrqISR, // IRQ

UnimplementedISR, // XIRQ

UnimplementedISR, // swi

UnimplementedISR, // unimplemented instruction trap

UnimplementedISR, // COP failure reset

UnimplementedISR // clock monitor fail reset

/*_startup, by default in library*/ // reset vector

};