Instruction Set Reference - The HCS12/9S12: An Introduction to Software and Hardware Interfacing - page 818

long2alpha(temp,buf); /* convert the 32-bit number to an ASCII string */

putsr(&buf[0]); /* output the converted string */

newline();

return 0;

}

▲

Example E.2
▼ Modify the C program in Example 6.5 so that it can be compiled using the GNU C com-
piler and run in a demo board programmed with the D-Bug12 monitor.
Solution: EGNU does not support flash programming and hence it relies on the D-Bug12 moni-
tor to set the interrupt vector in SRAM. This program uses inline assembly instructions to set
up the interrupt vector for the RTI. The user also needs to include the SetClk.c file into the
project when compiling the program. The following program will run without modification on
the Dragon12-Plus demo board:
; ******************************************************************************
// This program is written for the EGNU C compiler.
; ******************************************************************************
#include “c:\egnu\include\hcs12.h”
#include “c:\egnu\include\vectors12.h”
#include “c:\egnu\include\SetClk.h”
#define INTERRUPT_attribute_((interrupt))
void INTERRUPT rtiISR(void);
int seq,ix,count;
char segPat[13] 5 {0x06,0x5B,0x4F,0x66,0x6D,0x7D,0x07,0x7F,0x67,0x3F,0x06,0x5B,0x4F};
char digit[4] 5 {0xFE,0xFD,0xFB,0xF7};
void main (void) {

asm(“ldd #rtiISR”);

asm(“pshd”);

asm(“ldd #56”);

asm(“ldx 0xEEA4”);

asm(“jsr 0,x”);

seq 5 0;

ix 5 0;

count 5 400;

SetClk8();

RTICTL 5 0x40; // RTI interrupt interval set to 2**10 OSCCLK cycles

DDRB 5 0xFF; // configure Port B for output

DDRP 5 0xFF; // configure Port P for output

CRGINT | 5 RTIE; // enable RTI interrupt

asm(“CLI”); //enable interrupt globally

while(1);

}
void INTERRUPT rtiISR(void) {

CRGFLG 5 0x80; // clear RTIF bit