Internal Memory Configuration and External Expansion - The HCS12/9S12: An Introduction to Software and Hardware Interfacing - page 752

The elapsed time before the data bus signal degrades to an invalid level can be estimated by
the following equation:
D t < C D V 4 I
The voltage degradation of 2.5 V (for a 5-V V CC ) is considered enough to cause data input to
the SRAM to change the logic value from 1 to 0. The data bus line on the printed circuit board
is normally not longer than 1 ft for a single-board computer, so 1 ft will be used as its length.
The elapsed time before the data bus signal degrades to an invalid level is
D t < 20 pF 3 2.5 V 4 22.5 μ A < 2.2 μ s
Although this equation is oversimplified, it does give some idea about the order of the time
over which the charge across the data bus capacitor will hold after the HCS12 stops driving the
data bus. Even if the leakage current is 10 times larger, the

t value will be 225 ns and is still
longer than the minimum hold-time requirement of the K5R1008C1D.

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Example 14.18
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For the circuit shown in Figure 14.46, can the EEPROM be accessed without stretching the
E-clock, assuming that the 120-ns access time version of the AT28C010 is used? If not, how
many cycles should the E-clock be stretched?
Solution: The timing analysis of this problem differs from that of the SRAM mainly in the read/
write data setup times. According to the analysis done in Example 14.16, A16, . . . , A0 become valid
the latest (30.5 ns after the start of a read cycle). The data output from the AT28C010 becomes valid
150.5 ns after the start of a read cycle. For a 25-MHz E-clock, this is 110.5 ns (150.5 ns - 40 ns) too
late from the end of a read cycle. Therefore, the read cycle for the AT28C010 needs to be stretched
for at least three E-clock periods at this frequency. After stretching the E-clock by three cycles, the
read data is valid 9.5 ns before the end of the read cycle. This doesn't provide enough data setup time
for the HCS12. The only solution is to lower the frequency of the E-clock. By slowing the E-clock
frequency to 24 MHz, the read data setup time is increased to 16.17 ns and satisfies the require-
ment. The AT28C010 provides 0 ns of data hold time, which is acceptable for the HCS12.
According to Example 14.16, the HCS12 provides 17.5 ns of write data setup time, which is
shorter than the requirement (50 ns minimum) of the AT28C010. Stretching the E-clock by one
E-clock period can satisfy this requirement. However, the write pulse width (both the EEPROM_CS
and WE0) must be at least 100 ns. This would require the write bus cycle to be stretched by at
least two E-clock periods. Since the read cycle needs to be stretched by three E-clock periods, the
EBICTL and MISC registers need to be programmed to provide this requirement.

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Example 14.19
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Write an instruction sequence to configure the EBICTL and MISC registers to stretch the
external bus cycles by three E-clock periods.
Solution: The value to be written into the EBICTL is $01. This value enables the E-clock stretch.
The value to be written into the MISC register is $0D, which will stretch the bus cycles by
three E-clock periods. The following instruction sequence will achieve the required stretching:
movb #$01,EBICTL ; enable E stretch

movb #$0D,MISC ; stretch E by 3 periods

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