Internal Memory Configuration and External Expansion - The HCS12/9S12: An Introduction to Software and Hardware Interfacing - page 751

O UTPUT -E NABLE S IGNAL T IMING
The OE signal is the complement of the R/W signal and is generated by the GAL16V8. The
R/W signal is valid 7 ns after the start of a bus cycle. Therefore, the OE signal will become valid
10.5 ns after the start of a bus cycle and become invalid 5.5 ns after the end of a bus read cycle.

R EAD C YCLE T IMING V ERIFICATION
For the K6R1008C1D SRAM, address inputs A16,A0 become valid later than OE and CS.
Therefore, read data is valid 30.5 ns after the start of a read cycle or 9.5 ns before the end of a
read cycle. The HCS12DP256 requires a read data setup time of 13 ns. Therefore, the read data
does not provide enough setup time for the HCS12DP256 to correctly read it. One needs to
stretch the E-clock by one period.

W RITE C YCLE T IMING V ERIFICATION
The address inputs to the K6R1008C1D will stay valid until the new address is latched in
the next bus cycle. Therefore, A16,A0 stay valid for a whole E-clock period (40 ns at 25 MHz)
and satisfy the minimum requirement 10 ns ( t WC ).
The write-enable signals WE1 and WE0 have a low pulse width of 21.5 ns (40 ns 2 24 ns 1
5.5 ns) and satisfy the requirement of the SRAM.
The HCS12 drives the write data 28 ns after the start of a write cycle (or 12 ns before the
end of a write cycle). Both the WE and CS signal inputs to the K5R1008C1D are deasserted
5.5 ns after the end of a write cycle. This provides 17.5 ns of write data setup time for the
K5R1008C1D and exceeds the minimum requirement of 5 ns. The K5R1008C1D requires a
write data hold time of 0 ns. Since the CS and WE signals become invalid 5.5 ns after the end
of a write cycle. The write data must remain valid for at least 5.5 ns after a write cycle. The
HCS12 stops driving the write data 2 ns after the end of a write bus cycle. This is shorter than
the requirement. However, the HCS12 does not drive the multiplexed address/data bus for 8 ns
after the start of the next bus cycle. During this period, the capacitance of the printed circuit
board can keep the write data for a little while longer and satisfies the write data hold-time
requirement. Because both the write data setup- and hold-time requirements are satisfied, the
E-clock needs not be stretched for the write cycle.
Because the E-clock stretching applies to all the bus cycles, both the read and write cycles
need to be stretched for one E-clock period for the K5R1008C1D.

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Example 14.17
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Provide an analytical proof that the capacitance of the printed circuit board can hold the
data voltage for enough time to satisfy the data hold-time requirement of the SRAM.
Solution: The voltage of the data input to the K5R1008C1D is degraded by the following leakage
currents:
1. Input current into the HCS12 data pin (typically on the order of 2.5 μ A for Freescale

microcontroller products)
2. Input current into the EEPROM chips (on the order of 10 μ A)

A)
The capacitance of the printed circuit board is estimated to be 20 pF per foot. Let C , I ,

3. Other leakage paths (assumed to be as large as 10 μ

Δ V , and

Δ t be the printed circuit board capacitance of one data line, total leakage current, voltage change

due to leakage current, and the time it takes for the voltage to degrade by Δ V , respectively.