Internal Memory Configuration and External Expansion - The HCS12/9S12: An Introduction to Software and Hardware Interfacing - page 749

14.10.4 Write-Control Signals
Because the HCS12 may sometimes write to a byte rather than a word of the external mem-
ory, the WE signal for the upper byte (even address) and lower byte (odd address) must be gener-
ated separately. Let WE1 and WE0 be the write-enable signals of the high and low bytes; then
WE1 5 !(LSTRB * !A0 * !R/W 1 LSTRB* !A0 * !R/W) 5 !(!A0 * !R/W)
WE0 5 !(LSTRB * A0 * !R/W 1 LSTRB * A0 * !R/W) 5 !(A0 * !R/W)
These two control signals can be generated by using an inverter chip and a NAND gate
chip. A simpler solution is to generate the chip-select signals and write-enable signals using a
single GAL device, such as the GAL16V8. The GAL16V8 has a propagation delay of 3.5 ns. By
using a GAL16V8 to generate the chip-select and write-enable signals as shown in Figure 14.45,
the decoder circuit shown in Figure 14.44 can be eliminated. In Figure 14.45, the output-enable
signal (OE) required to control the output of SRAM and EEPROM can be generated without ad-
ditional cost. The OE signal is simply the complement of the R/W signal output of the HCS12.

A0 SRAM_CS

EEPROM_CS

W

ECS GAL16V8

WE1

XA18 WE2

XA19 OE

Figure 14.45 ■ Address decoder and
write-enable signal-generating circuit

The design of the circuit shown in Figure 14.45 can be done by using the ispLEVER soft-
ware from Lattice Semiconductor.

14.10.5 Example HCS12 External Memory Design
As shown in Figure 14.46, the circuit required to interface with external SRAMs and EEPROMs
is minimal. A 16-bit latch is needed to keep address signals A15,A0 valid throughout the whole
bus cycle. A GAL16V8 chip is us ed to generate the chip-select signals for selecting the SRAM
and EEPROM modules. The ECS signal is asserted (goes low) only when the address outputs are
valid. It must be included as one of the inputs to the address decoder circuit to make sure that the
decoder asserts one of its outputs to low when its address inputs XA18 and XA19 are valid.

Example 14.16
▼

For the circuit shown in Figure 14.46, can the SRAM be accessed without stretching the
E-clock? Assume that the E-clock is 25 MHz.
Solution: The timing verification consists of the read cycle and the write cycle.

A DDRESS T IMING
The address inputs A12, . . . , A0 to the memory chips become valid 20.5 ns after the start
of a bus cycle; the address inputs A16, . . . , A13 become valid 6 ns after the start of a bus cycle.