Hardware Reference
In-Depth Information
At 25 MHz, address signals A15, . . . , A0 (driven by the HCS1 2) be come valid 8 ns after the
falling edge of the E-clock or up to 8 ns before the falling edge of the ECS signal. Since A15, . . . , A0
stay valid until 2 ns after the rising edge of the E-clock, A15, . . . , A0 have a hold time of at least
6 ns. Therefore, the input-setup and hold-time requirements of the 74ABT16373B are satisfied.
Since the propagation delay relative to the 1E and 2E signals is 4.4 ns, A15, . . . , A0 will become
valid (to memory chips) 0.4 ns after the rising edge of the E-clock or 20.4 ns after the start of a bus
cycle. The address latching circuit is shown in Figure 14.43.
74ABT16373B
ECS
1E
2E
A15 , A0
A15/D15 , A0/D0
1OE
2OE
Figure 14.43 Address latch circuit for the HCS12
The latched outputs A0, A14, and A15 are not used in a paged memory module. A0 is not
used because the memory module is 16 bit.
14.10.3 Address Decoder Design
In this simple memory design example, the 1-MB memory space is divided into four 256-kB
modules. Therefore, the highest 2 address bits, XA19 and XA18, should be used as decoder
inputs. A 3-to-8 decoder (e.g., 74F138) or a dual 2-to-4 decoder (e.g., 74F139) can be used as the
address decoder. The chip-select signal equations for the SRAM and EEPROM are
SRAM_CS 5 !(!XA19 * !XA18 * ECS)
EEPROM_CS 5 !(!XA19 * XA18 * ECS)
The decoder circuit is shown in Figure 14.44.
5 V
74F138
E1
E2
E3
SRAM_CS
Y0
ECS
Y1
EEPROM_CS
XA18
XA19
A0
A1
A2
Figure 14.44 HCS12 external memory
decoder circuit
 
 
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