Hardware Reference
In-Depth Information
The AT28C010 allows the designer to poll the I/O7 pin to find out if an internal write operation
has completed. Before an internal write operation has completed, a read of the last byte written
will result in the complement of the written data being presented on the I/O7 pin. Once the write
cycle has been completed, true data is valid on all outputs, and the next write cycle can begin.
In addition to data polling, the AT28C010 provides another method for determining the end
of a write cycle. During the internal write operation, successive attempts to read data from the
device will result in I/O6 toggling between 1 and 0. Once the write operation has completed,
the I/O6 pin will stop toggling, and valid data will be read.
D
ATA
P
ROTECTION
Atmel has incorporated both hardware and software features to protect the memory against
inadvertent write operations. The hardware protection method works as follows:
•
V
CC
sense
. If
V
CC
is below 3.8 V, the write function is inhibited.
•
V
CC
power-on delay
. Once
V
CC
has reached 3.8 V, the device will automatically
time out for 5 ms before allowing a write operation.
•
Write inhibit
. Holding the OE signal low or the CE signal high or the WE signal
high inhibits write cycles.
•
Noise filter
. Pulses shorter than 15 ns on the WE or the CE input will not initiate a
write cycle.
A software data protection (SDP) feature is included that can be enabled to prevent
inadvertent write operations. The SDP is enabled by the host system issuing a series of three
write commands; 3 specific bytes of data are written to three specific addresses. After writing
the 3-byte command sequence and after the
t
WC
delay, the entire AT28C010 will be protected
against inadvertent write operations. It should be noted that once protected, the host may still
perform a byte write or page write to the AT28C010. This is done by preceding the data to be
written by the same 3-byte command sequence used to enable the SDP. Once set, the SDP will
remain active unless the disable command sequence is issued. Power transitions do not disable
the SDP, and the SDP will protect the AT28C010 during the power-up and power-down condi-
tions. After setting the SDP, any attempt to write to the device without the 3-byte command
sequence will start the internal write timer. No data will be written into the device.
The algorithm for enabling software data protection is as follows:
Step 1
Write the value of 0xAA to the memory location at 0x5555.
Step 2
Write the value of 0x55 to the memory location at 0x2AAA.
Step 3
Write the value of 0xA0 to the memory location at 0x5555. At the end of write, the write-
protect state will be activated. After this step, write operation is also enabled.
Step 4
Write any value to any location (1-128 bytes of data are written).
Step 5
Write last byte to last address.
Software data protection can be disabled any time when it is undesirable. The algorithm for
disabling software data protection is as follows:
Step 1
Write the value of 0xAA to the memory location at 0x5555.
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