Hardware Reference
In-Depth Information
1
32
NC
V
cc
2
31
A16
WE
3
30
NC
A15
4
29
A12
A14
5
28
A7
A13
6
27
A6
A8
26
A5
7
A9
8
25
A4
A11
AT28C010
24
A3
9
OE
10
23
A2
A10
11
22
A1
CE
12
21
A0
I/O7
13
20
I/O0
I/O6
14
19
I/O1
I/O5
13
18
I/O2
I/O4
14
17
GND
I/O3
Figure 14.38
■
The AT28C010 pin assignment
D
EVICE
O
PERATION
The AT28C010 is accessed like a SRAM. When the CE and OE signals are low and the WE signal
is high, the data stored at the location determined by the address pins is driven on the I/O pins. The
I/O pins are put in the high-impedance state when either the CE or OE signal is high.
A byte-write operation is started by a low pulse on the WE or the CE input with the CE or
the WE input low (respectively) and the OE pin high. The address inputs are latched on the fall-
ing edge of the CE or the WE signal, whichever occurs last. The data is latched by the first rising
edge of the CE or the WE signal.
A page-write operation is initiated in the same manner as a byte-write operation; after
the first byte is written, it can then be followed by 1 to 127 additional bytes. Each successive
byte must be loaded within 150
s (
t
BLC
) of the previous byte. If the
t
BLC
limit is exceeded, the
AT28C010 will cease accepting data and begin the internal programming operation. All bytes
involved in a page-write operation must reside on the same page as defined by the state of the
A16, . . . , A7 inputs. For each high-to-low transition of the WE signal during the page-write
operation, the address signals A16-A7 must be the same. The inputs A6-A0 are used to specify
which bytes within the page are to be written. The bytes may be loaded in any order and may be
altered within the same load period. Only bytes that are specified for writing will be written.
μ
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