Hardware Reference
In-Depth Information
t WC
Address
t WR
t AW
OOE
t CW
CCS
t AS
t WP
WWE
t DW
t DH
Data In
Valid data
t OHZ
High Z
Data Out
Figure 14.37a K6R1008C1D write cycle timing diagram
t WC
Address
t AW
t WR
t CW
CCS
t AS
t WP
WWE
t DW
t DH
Data In
Valid data
t WHZ
t OW
High Z
Data Out
Figure 14.37b K6R1008C1D write cycle timing diagram (OE tied to low)
The device utilizes internal error correction for extended endurance and improved data re-
tention. To prevent an unintended write operation, an optional software data protection mech-
anism is available. The device also includes an additional 128 bytes of EEPROM for device
identification or tracking. The pin assignment for the AT28C010 is shown in Figure 14.38.
 
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