Internal Memory Configuration and External Expansion - The HCS12/9S12: An Introduction to Software and Hardware Interfacing - page 707

The CCIF flag indicates that there are no more commands pending. The CCIF flag is cleared
when CBEIF is cleared and sets automatically on completion of all active and pending com-
mands. Writes to the CCIF flag have no effect.
The PVIOL flag indicates an attempt was made to program or erase an address in a protected
flash memory area. The PVIOL flag is cleared by writing a 1 to it. Writing a 0 has no effect.
The ACCERR flag indicates an illegal access to the selected flash array. This can be a viola-
tion of the command sequence, issuing an illegal command, or the execution of a CPU STOP
instruction while a command is executing. This flag is cleared by writing a 1 to it. Writing a 0
to the ACCERR flag has no effect.

F LASH C OMMAND R EGISTER (FCMD)
This register defines the flash commands. This register is banked; its contents are shown
in Figure 14.15.

7 6 5 4 3 2 1 0

0 CMDB6 CMDB5 0 0 CMDB2 0 CMDB0 base+$106

Reset: 1 1 0 0 0 0 0 0

CMDB6, CMDB5, CMDB2, and CMDB0: command bits
Valid commands include the following:
$05 = erase and verify.
$20 = program a word (2 bytes).
$40 = sector erase.
$41 = bulk erase.

Figure 14.15 ■ Flash command register (FCMD)

To perform these commands, we must make sure that the following prerequisites are
satisfied:
1. The FCLKDIV register has been configured correctly.
2. The sector to be erased is not be protected.
3. The flash word to be programmed has been erased and not be protected.
4. The first flash address is word aligned (A0 5 0).
5. If the flash address is in the range of $8000 to $BFFF, then the PPAGE register has been
written to select the desired page.
6. If the MCU has multiple flash blocks, the ACCERR and PVIOL flags in all blocks
have been cleared.
7. The BSEL bits in the FCNFG register have been written to select the desired block to
be programmed or erased.

F LASH 16-B IT A DDRESS R EGISTER (FADDRHI AND FADDRLO)
Bit 15 of the address register is tied to 0. In normal modes, the FADDR register reads zero
and is not writable. The FADDRHI and FADDRLO registers can be written in special modes by
writing to the address base1$108 and base1$109 in the register space.

F LASH 16-B IT D ATA B UFFER AND R EGISTER (FDATA)
In normal modes, all FDATA bits read zero and are not writable. In special modes, all FDATA
bits are readable and writable when writing to an address within the flash address range.