Hardware Reference
In-Depth Information
Example 14.3
▼
What is the corresponding SRecAddr for the pair of (PageNum, PageWinAddr) equal to ($20,
$A003)?
Solution:
Apply Equation 14.3 as follows:
SRecAddr
5
$20
3
$4000 (16K)
1
$A003
2
$8000
5
$82003
▲
All HCS12 members have a certain amount of on-chip flash memory. The amount of
flash memory may be 32 kB, 64 kB, 128 kB, 256 kB, or 512 kB. A flash memory larger than
64 kB is divided into two or more 64-kB blocks. These 64-kB flash memory blocks can be
read, programmed, or erased concurrently.
The algorithms for erasing and programming flash memory require very little user involve-
ment. Programming and erasure are performed by sending commands to the command register.
Interrupts may be requested when a command is completed or when the command buffer is
empty. A two-stage command pipeline is implemented to accelerate the command execution.
The flash memory includes a flexible protection scheme against accidental programming and
erasure. The flash memory also implements security measures to prevent the application code
from being pirated.
The discussion of flash memory will be based on the 256-kB flash memory of several HCS12
members.
The memory map of the 256-kB flash memory is shown in Figure 14.8.
The entire flash memory is divided into pages of 16 kB in size. One page is always accessible
at $4000 to $7FFF and another fixed page is always accessible at $C000 to $FFFF. The memory
space from $0000 to $3FFF has been occupied by registers, EEPROM, and SRAM and hence is
not available for flash memory. As shown in Figure 14.8, the first 64 kB of the flash memory is
referred to as block 0 and is assigned page numbers $3C to $3F. The pages with addresses from
$4000 to $7FFF, $8000 to $BFFF, and $C000 to $FFFF are assigned the page numbers $3E, $3D,
and $3F, respectively. Even though it is unnecessary, one can access the pages in address ranges
of $4000 to $7FFF and $C000 to $FFFF via the page window.
Each flash block may be protected against accidental erasure or programming. Flash protec-
tion is controlled by a flash protection register (FPROT). For microcontrollers that have multiple
flash blocks, there is a separate flash protection register for each flash block. These flash protection
registers share a common address, with the active register selected by the bank select bits of the
flash configuration register (FCNFG). During the HCS12 reset sequence (execution of reset startup
routine), the flash protection registers for each flash block are loaded from the programmed bytes
within a flash block. For example, for the MC9S12DP256, the locations $FF0A, $FF0B, $FF0C, and
$FF0D store the protection information of blocks three, two, one, and zero, respectively.
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