Hardware Reference
In-Depth Information
7
6
5
4
3
2
1
0
REG_SW0
0
EEP_SW1
EEP_SW0
0
RAM_SW2
RAM_SW1 RAM_SW0
base+$1C
Reset:
--
--
--
--
--
--
--
--
REG_SW0: allocated system register space
0 = allocated system register space size is 1 kB.
1 = allocated system register space size is 2 kB.
EEP_SW1
,
EEP_SW0: allocated system EEPROM memory space
00 = 0 kB
01 = 2 kB
10 = 4 kB
11 = 8 kB
RAM_SW2
,
RAM_SW0: Allocated system RAM memory space
The allocated system RAM space size is as given in Table 14.2.
Figure 14.5
■
Memory size register zero (MEMSIZ0)
RAM_SW2:
RAM_SW0
Allocated RAM
Space
RAM Mappable
Region
INITRM Bits Used
RAM Reset Base
Address
1
000
001
010
011
100
101
110
111
2 kB
4 kB
6 kB
8 kB
10 kB
12 kB
14 kB
16 kB
2 kB
4 kB
8 kB
2
8 kB
16 kB
2
16 kB
2
16 kB
2
16 kB
RAM15
,
RAM11
RAM15
,
RAM12
RAM15
,
RAM13
RAM15
,
RAM14
RAM15
,
RAM14
RAM15
,
RAM14
RAM15
,
RAM14
RAM15
,
RAM14
$0800
$0000
$0800
$0000
$1800
$1000
$0800
$0000
1
The RAM reset base address is based on the reset value of the INITRM register, $09.
2
Alignment of the allocated RAM space within the RAM mappable region is dependent on the
value of RAMHAL.
Table 14.2
■
Allocated RAM memory space
M
EMORY
S
IZE
R
EGISTER
O
NE
(MEMSIZ1)
This register is read-only and reflects the state of the flash or ROM physical memory and
paging switches at the core boundary, which are configured at system integration. This register
allows read visibility to the state of these switches. The contents of this register are shown in
Figure 14.6. Table 14.3 shows that the HCS12 supports 1 MB of memory space.
7
6
5
4
3
2
1
0
ROM_SW1 ROM_SW0
0
0
0
0
PAG_SW1
PAG_SW0
base+$1D
--
--
--
--
--
--
--
--
Reset:
ROM_SW1
,
ROM_SW0: allocated system flash or ROM physical memory space
00 = 0 kB
01 = 16 kB
10 = 48 kB
11 = 64 kB
PAG_SW1
,
PAG_SW0: allocated off-chip flash or ROM memory space
The allocated off-chip flash or ROM memory space size is as given in Table
14.3.
Figure 14.6
■
Memory size register one (MEMSIZ1)
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