Hardware Reference
In-Depth Information
7
6
5
4
3
2
1
0
EE15
EE14
EE13
EE12
EE11
0
0
EEON
base+$12
Value after
reset:
0
0
0
1
0
0
0
1
EE15 , EE11: internal EEPROM map position
These bits specify the upper 5 bits of the 16-bit registers address.
These 5 bits can be written only once in normal modes and can be
written many times in special modes. There is no restriction on the
reading of this register.
EEON: internal EEPROM on (enabled reading).
0 = removes EEPROM from the map.
1 = places the on-chip EEPROM in the memory map.
Figure 14.3 Contents of the INITEE register
7
6
5
4
3
2
1
0
Reset value:
Expanded or
emulation
Peripheral or
single chip
Special test
0
0
0
0
EXSTR1
EXSTR0
ROMHM
ROMON
base+$13
1
0
0
0
0
1
1
0
0
0
0
0
1
1
0
1
0
0
0
0
1
1
0
0
EXSTR1 , EXSTR0: external access stretch bits 1 and 0
00 = no stretch to external bus cycle.
01 = stretch the external bus cycle by one E cycle.
10 = stretch the external bus cycle by two E cycles.
11 = stretch the external bus cycle by three E cycles.
ROMHM: flash EEPROM or ROM only in second half of memory map
0 = The fixed page(s) of flash EEPROM or ROM in the lower half of
the memory map can be accessed.
1 = Disable direct access to the flash EEPROM or ROM in the lower
half of the memory map. These physical locations of flash memory
can still be accessed through the program page window.
ROMON: enable flash memory or ROM
0 = disable the flash memory or ROM in the memory map.
1 = enable the flash memory or ROM in the memory map.
Note: 1. The reset state of this bit is determined at the chip integration level.
Figure 14.4 Contents of the MISC register
latched, then the on-chip flash memory is enabled and the reset startup routine will be executed
from the on-chip flash memory rather than from the external ROM. After reset, this pin is used
as the ECS signal. This register can only be written once in normal and emulation modes but
can be written any time in special modes.
M EMORY S IZE R EGISTER Z ERO (MEMSIZ0)
This register is read only. It reflects the size of the on-chip I/O register, EEPROM, and
SRAM. The contents of this register are shown in Figure 14.5. The allocated system register
space, EEPROM space, RAM memory space, and the RAM reset base address are summarized
in Table 14.2.
 
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