Hardware Reference
In-Depth Information
establish these resource locations during the initialization phase of program execution, even
if default values are chosen, in order to protect the registers from inadvertent modification
later. Writes to the mapping registers require one cycle to take effect. To ensure that there
are no unintended operations, a write to one of these registers should be followed by a NOP
instruction.
If conflict occurs when mapping resources, the register block will take precedence over
other resources; RAM or EEPROM addresses occupied by the register block will not be avail-
able for storage. When active, BDM ROM takes precedence over other resources, although
a conflict between BDM ROM and register space is not possible. Table 14.1 shows mapping
precedence. Only one module will be selected at a time. In the case of more than one module
sharing a space, only the module with the highest precedence will be selected. Mapping more
than one module to the same location won't damage the system. However, it is not wise to
map two or more modules to the same space because a significant amount of memory could
become unusable.
In expanded modes, all address space not used by internal resources is by default external
memory.
Precedence
Resource
1
2
3
4
5
6
BDM firmware or register space
Internal register space
SRAM block
EEPROM
Flash memory
Remaining external memory
Table 14.1
■
Mapping precedence
After reset, the register block (1 or 2 kB) can be remapped to any 2 kB space within the first
32 kB of the system address space. Mapping of internal registers is controlled by 4 bits in the
INITRG register. The contents of this register are shown in Figure 14.1. Only bit 6 to bit 3 are
implemented. The INITRG register can be written into once in normal mode but many times
in special modes.
7
6
5
4
3
2
1
0
0
REG14
REG13
REG12
REG11
0
0
0
base $11
Value after
reset:
0
0
0
0
0
0
0
0
REG14
,
REG11: internal register map position
These 4 bits along with bit 7 specify the upper 5 bits of the 16-bit
register address. These 4 bits can be written only once in normal
modes and can be written many times in special modes. There is no
restriction on the reading of this register.
Figure 14.1
■
Contents of the INITRG register
Search WWH ::
Custom Search