Controller Area Network (CAN) - The HCS12/9S12: An Introduction to Software and Hardware Interfacing - page 688

bit time to the recessive-to-dominant edge of the transmitted start of frame. Resynchronization
is performed during the remainder of the frame, whenever a change of bit value from recessive
to dominant occurs outside of the expected sync_seg segment.
A CAN module (also called CAN controller) requires a CAN bus transceiver, such as the
Philips PCA82C250 or the Microchip MCP2551, to interface with the CAN bus. Most CAN
controllers allow more than 100 nodes to connect to the CAN bus. The CAN trunk cable could
be a shielded cable, unshielded twisted pair, or simply a pair of insulated wires. It is recom-
mended that shielded cable be used for high-speed transfer when there is a radio frequency
interference problem. Up to a 1-Mbps data rate is achievable over a distance of 40 m.
The CAN module of the HCS12 MCU has six major modes of operation.
• Initialization mode
• Disable mode
• Normal operation mode
• Listen-only mode
• Loopback mode
• Sleep mode
• Stop mode
All configuration operations can only be performed in the initialization mode. Designers
must make sure that the initialization mode is entered before performing the configuration.
Most CAN parameters are configured immediately after reset. However, applications may need
to change the configuration during the normal operation. Under this situation, the designer will
need to put the CAN into sleep mode before performing reconfiguration. The first step in CAN
configuration is to initialize the timing parameters. The procedure for doing this is described
in Section 13.12. All data transfer and reception with other nodes are performed in the normal
operation mode.
The CAN module has three transmit buffers and five receive buffers. The first 13 bytes of
a transmit buffer and a receive buffer are identical. In addition, the transmit buffer also has a
transmit buffer priority register and two transmit timestamp registers. One of the three trans-
mit buffers is mapped to the foreground transmit buffer space and is made accessible to the
designer. Five receive buffers are organized as a FIFO, and only the head of the FIFO is mapped
to the receive foreground space and becomes accessible to the designer.
Each transmit and receive buffer has eight data registers for holding data, four identifier
registers for identification and arbitration purposes, and one length-count register for indicating
the number of data segment registers that contain valid data. Data transmission involves copy-
ing data into identifier registers, data segment registers, and the data length register, setting the
priority of the transmit buffer, and clearing the transmit buffer empty bit to mark the buffer
ready for transmission. Data reception in the CAN bus is often interrupt-driven due to the un-
predictability of message arrival times.
13.15 Exercises
E13.1 Calculate the bit segments for the following system constraints assuming that the
Microchip MCP2551 transceiver is used:
Bit rate 5 400 kbps
Bus length 5 50 m