Controller Area Network (CAN) - The HCS12/9S12: An Introduction to Software and Hardware Interfacing - page 686

CAN1BTR0 5 0xC7; // set SJW to 4, set prescaler to 8

CAN1BTR1 5 0xB4; // set phase_seg2 to 4 t Q , phase_seg1 to 4 t Q ,

// prop_seg to 1 t Q

CAN1IDAR0 5 0x56; // set acceptance identifier V1

CAN1IDAR1 5 0x3C; // “

CAN1IDAR2 5 0x40; // “

CAN1IDAR3 5 0x00; // “

CAN1IDMR0 5 0x00; // acceptance mask for V1

CAN1IDMR1 5 0x00; // “

CAN1IDMR2 5 0x3F; // “

CAN1IDMR3 5 0xFF; // “

CAN1IDAR4 5 0x56; // set acceptance identifier V1

CAN1IDAR5 5 0x3C; // “

CAN1IDAR6 5 0x40; // “

CAN1IDAR7 5 0x00; // “

CAN1IDMR4 5 0x00; // acceptance mask for V1

CAN1IDMR5 5 0x00; // “

CAN1IDMR6 5 0x3F; // “

CAN1IDMR7 5 0xFF; // “

CAN1IDAC 5 0x00; // select two 32-bit filter mode

CAN1CTL0 5 0x25; // stop clock on wait mode, enable wake-up

CAN1CTL0 & 5 , INITRQ; /* exit initialization mode */

}
void snd2can1(char *ptr)
{
int tb,i,*pt1,*pt2;
pt1 5 (int *)ptr; /* convert to integer pointer */

while(1) {

if(CAN1TFLG & TXE0){

tb 5 0;

break;

}

if(CAN1TFLG & TXE1){

tb 5 1;

break;

}

if(CAN1TFLG & TXE2){

tb 5 2;

break;

}

}

CAN1TBSEL 5 CAN1TFLG; // make empty transmit buffer accessible

pt2 5 (int *)&CAN1TIDR0; // pt2 points to the IDR0 of TXFG

for (i 5 0; i < 7; i 11 ) // copy the whole transmit buffer

*pt2 11 5 *pt1 11 ;

if (tb 55 0)

CAN1TFLG 5 TXE0; // mark buffer 0 ready for transmission