Hardware Reference
In-Depth Information
NRZ signal
Time segment 1
(prop_seg + phase_seg1)
Time segment 2
(phase_seg2)
SYNC_SEG
1
4 16
2 8
8 25 time quanta
= 1 bit time
Sample point
(single or triple sampling)
Transmit point
Figure 13.40 Segments within the bit time
The bit rate of the CAN bus can be derived from the frequency of the time quantum using
the following expression:
Bit rate 5 f t Q ÷ (number of time quanta)
By computing the number of time quanta contained in a bit time, we can figure out the ap-
propriate values for time segment 1 and time segment 2. This will be elaborated in Section 13.12.
13.9.7 MSCAN Interrupt Operation
The MSCAN supports four interrupt vectors, any of which can be individually masked.
T RANSMIT I NTERRUPT
At least one of the three transmit buffers is empty and can be loaded to schedule a message
for transmission. The TXEx flag of the empty message buffer is set.
R ECEIVE I NTERRUPT
A receive interrupt may be requested when a message is successfully received and shifted
into the foreground buffer of the receive FIFO. This interrupt is generated immediately after
receiving the EOF symbol. The RXF flag is set. If there are multiple messages in the receiver
FIFO, the RXF flag is set as soon as the next message is shifted to the foreground buffer.
W AKE -U P I NTERRUPT
Activity on the CAN bus occurring during the MSCAN internal sleep mode may generate
the wake-up interrupt.
E RROR I NTERRUPT
An overrun of the receiver FIFO, error, warning, or bus-off condition may generate an error
interrupt.
I NTERRUPT A CKNOWLEDGE
Interrupts are directly associated with one or more status flags in either the CAN x RFLG
or the CAN x TFLG register. Interrupts are pending as long as one of the corresponding flags is
set. The flags in these registers must be cleared within the interrupt handler to avoid repeated
interrupts. The flags are cleared by writing a 1 to the corresponding bit position. A flag cannot
be cleared if the respective condition still prevails.
 
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