Hardware Reference
In-Depth Information
Tx0
TXE0
PRIO
Tx1
TXE1
MSCAN
CPU bus
PRIO
Tx2
TXE2
PRIO
Figure 13.37 User model for transmit buffer organization
highest priority and is scheduled for transmission first. The internal scheduling process takes
place whenever the MSCAN arbitrates for the bus.
When a high-priority message is scheduled by the application, it may be necessary to abort
a lower-priority message in one of the three transmit buffers. A message that is being transmit-
ted cannot be aborted. One can make an abort request by setting an appropriate ABTRQ bit of
the CAN x TARQ register. The MSCAN then grants the request, if possible, by (1) setting the
corresponding Abort Acknowledge flag (ABTAK) in the CAN x TAAK register, (2) setting the
associated TXE flag to release the buffer, and (3) generating a transmit interrupt. The transmit
interrupt handler software can tell from the setting of the ABTAK flag whether the message was
aborted (ABTAK 5 1) or sent (ABTAK 5 0).
13.9.4 Receive Storage Structure
As shown in Figure 13.38, the received messages are stored in a five-stage input FIFO data
structure. The message buffers are alternately mapped into a single memory area, which is
referred to as the foreground receive buffer . The application software reads the foreground re-
ceive buffer to access the received message. The background receive buffer is solely used to hold
incoming CAN messages and is not accessible to the user.
 
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