Hardware Reference
In-Depth Information
expressed as a multiple of a
minimum time quantum
. This multiple is a programmable prescale
factor. Thus, the time quantum can have the length of
Time quantum
5
M
3
minimum time quantum
where
M
is the value of the prescaler.
The segments of a nominal bit time can be expressed in the unit of time quantum as follows:
•
sync_seg
is 1 time quantum long.
•
prop_seg
is programmable to be 1, 2, . . . , 8 time quanta long.
•
phase_seg1
is programmable to be 1, 2, . . . , 8 time quanta long.
•
phase_seg2
is the maximum of
phase_seg1
and information processing time and
hence will be programmable from 2 to 8
t
Q
.
•
The information processing time is equal to or less than 2
t
Q
and is fixed at 2
t
Q
for
the HCS12 CAN module.
The total number of time quanta in a bit time must be programmable over a range of at
least 8 to 25.
All CAN nodes must be synchronized while receiving a transmission; that is, the begin-
ning of each received bit must occur during each node's
sync_seg
segment. This is achieved
by synchronization. Synchronization is required because of phase errors between nodes, which
may arise because of nodes having slightly different oscillator frequencies or because of changes
in propagation delay when a different node starts transmitting.
Two types of synchronization are defined:
hard synchronization
and
resynchronization
.
Hard synchronization is performed only at the beginning of a message frame, when each CAN
node aligns the
sync_seg
of its current bit time to the recessive to dominant edge of the trans-
mitted start-of-frame field. After a hard synchronization, the internal bit time is restarted with
sync_seg
.
Resynchronization is subsequently performed during the remainder of the message
frame whenever a change of bit value from recessive to dominant occurs outside of the expected
sync_seg
segment. Resynchronization is achieved by implementing a digital phase-lock loop
(DPLL) function that compares the actual position of a recessive-to-dominant edge on the bus
to the position of the expected edge.
There are three possibilities for the occurrence of the incoming recessive-to-dominant edge.
1.
After the sync_seg segment but before the sample point
. This situation is interpreted
as a
late edge
. The node will attempt to resynchronize to the bitstream by increasing
the duration of its phase_seg1 segment of the current bit by the number of time
quanta by which the edge was late, up to the resynchronization jump width limit.
2.
After the sample point but before the sync_seg segment of the next bit
. This situation
is interpreted as an
early bit
. The node will now attempt to resynchronize to the
bitstream by decreasing the duration of its
phase_seg2
segment of the current bit by
the number of time quanta by which the edge was early, up to the resynchronization
jump width limit. Effectively, the
sync_seg
segment of the next bit begins immediately.
3.
Within the sync_seg segment of the current bit time
. This is interpreted as no
synchronization error.
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