Hardware Reference
In-Depth Information
Interframe space
or
Overload fr a me
Data
frame
Error frame
Error flag
Error delimiter
Superposition of
error flags
Figure 13.8 Error frame
an error-passive receiver). Therefore, the bus should not be loaded to 100 percent. An error-
passive node has an error count greater than 127 but no more than 255. An error-active node
has an error count less than 127. There are two forms of error flags.
Active-error flag . This flag consists of 6 consecutive dominant bits.
Passive-error flag. This flag consists of 6 consecutive recessive bits unless it is
overwritten by dominant bits from other nodes.
An error-active node signals an error condition by transmitting an active-error flag. The
error flag's form violates the law of bit stuffing (to be discussed shortly) and applies to all fields
from start of frame to CRC delimiter or destroys the fixed-form ACK field or end-of-frame field.
As a consequence, all other nodes detect an error condition and each starts to transmit an error
flag. Therefore, the sequence of dominant bits, which can be monitored on the bus, results from
a superposition of different error flags transmitted by individual nodes. The total length of this
sequence varies between a minimum of 6 and a maximum of 12 bits.
An error-passive node signals an error condition by transmitting a passive-error flag. The
error-passive node waits for 6 consecutive bits of equal polarity, beginning at the start of the
passive-error flag. The passive-error flag is complete when these equal bits have been detected.
The error delimiter consists of 8 recessive bits. After transmission of an error flag, each
node sends recessive bits and monitors the bus until it detects a recessive bit. Afterward, it
starts transmitting 7 more recessive bits.
13.3.4 Overload Frame
The overload frame contains two bit fields: overload flag and overload delimiter . There are
three different overload conditions that lead to the transmission of an overload frame.
1. The internal conditions of a receiver require a delay of the next data frame or remote
frame.
2. At least one node detects a dominant bit during intermission.
3. A CAN node samples a dominant bit at the eighth bit (i.e., the last bit) of an error
delimiter or overload delimiter. The error counters will not be incremented.
The format of an overload frame is shown in Figure 13.9. An overload frame resulting
from condition 1 is only allowed to start at the first bit time of an expected intermission,
whereas an overload frame resulting from overload conditions 2 and 3 starts 1 bit after detect-
ing the dominant bit.
 
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