Controller Area Network (CAN) - The HCS12/9S12: An Introduction to Software and Hardware Interfacing - page 638

DLC3 DLC2 DLC1 DLC0 Data Byte Count

d
d
d
d
d
d
d
d
r

d
d
d
d
r
r
r
r
d

d
d
r
r
d
d
r
r
d

d
r
d
r
d
r
d
r
d

0
1
2
3
4
5
6
7
8

Note: d = dominant, r = recessive.

Table 13.1 ■ CAN data length coding

D ATA F IELD
The data field consists of the data to be transmitted within a data frame. It may contain
from 0 to 8 bytes, each of which contains 8 bits that are transferred most significant bit first.

CRC F IELD
The CRC field contains the CRC sequence followed by a CRC delimiter, as shown in
Figure 13.5. The frame-check sequence is derived from a cyclic redundancy code best suited
to frames with bit counts less than 127. The CRC sequence is calculated by performing a
polynomial division. The coefficients of the polynomial are given by the destuffed bit stream,
consisting of the start-of-frame field, arbitration field, control field, data field (if present), and
15 0s. This polynomial is divided (the coefficients are calculated using modulo-2 arithmetic)
by the generator polynomial
X 15 1 X 14 1 X 10 1 X 8 1 X 7 1 X 4 1 X 3 1 1

Data or
control field ACK

CRC field

CRC sequence CRC delimiter

Figure 13.5 ■ CRC field

The remainder of this polynomial division is the CRC sequence. In order to implement
this function, a 15-bit shift register CRC_RG (14:0) is used. If nxtbit denotes the next bit of the
bit stream, given by the destuffed bit sequence from the start of frame until the end of the data
field, the CRC sequence is calculated as follows:
CRC_RG 5 0; /* initialize shift register */

do {

crcnxt 5 nxtbit ^ CRC_RG(14); /* exclusive OR */

CRC_RG(14:1) 5 CRC_RG(13:0); /* shift left by 1 bit */

CRC_RG(0) 5 0;
if crcnxt
CRC_RG(14:0) 5 CRC_RG(14:0) ^ 0x4599;
} while (!(CRC SEQUENCE starts or there is an error condition));