Analog-to-Digital Converter - The HCS12/9S12: An Introduction to Software and Hardware Interfacing - page 629

• Unsigned result representation
• A/D result left-justified, single conversion sequence
• Perform eight conversions in a sequence
• Enable fast flag clear, non-FIFO mode
• Disable the ATD interrupt
• Power down ATD in wait mode
• In background debug mode, finish current conversion, then freeze
• 10-bit resolution, eight clock periods second-stage sample time, prescaler set to 8
E12.8 Write an instruction sequence to confi gure the HCS12DP256 A/D converter with the fol-
lowing characteristics:
• f OSC 5 8 MHz
• Channel AN0,AN3
• A/D result right-justified
• 8-bit resolution, unsigned result, continuous conversion
• Four conversions in a sequence
• Prescaler set to 2
• Four cycles second-stage sample time, non-FIFO mode
• Enable fast ATD flag clear, enable ATD interrupt
• External falling edge triggered (at ATD7 pin)
• Finish current conversion then freeze in background debug mode
E12.9 Assuming that S8C,S1C (ATD0CTL3) are set to 0111 and CC,CA (ATD0CTL5) are set
to 101, what is the conversion sequence for this setting?
E12.10 Assume that the following setting was programmed before a new conversion is started:
• The conversion counter value in the ATD0STAT0 register is 4.
• The channel-select code of the ATD0CTL5 is 7.
• The conversion sequence limit of the ATD0CTL3 register is set to 6.
• The MULT bit of the ATD0CTL5 register is set to 1.
How would the conversion results be stored when the FIFO mode is selected or not selected?
E12.11 Assume that the following setting was programmed before a new conversion is started:
• The conversion counter value in the ATD0STAT0 register is 3.
• The channel-select code of the ATD0CTL5 is 5.
• The conversion sequence limit of the ATD0CTL3 register is set to 4.
• The MULT bit of the ATD0CTL5 register is set to 1.
How would the conversion results be stored when the FIFO mode is selected or not selected?
E12.12 At 8-bit resolution with the second-stage sampling time set to eight ATD clock cycles,
how long does it take to complete the conversion of one sample at 500 kHz and at 2 MHz ATD
clock frequencies, respectively?
E12.13 At 10-bit resolution with the second stage sampling time set to four ATD clock cycles,
how long does it take to complete the conversion of one sample at 500 kHz and 2 MHz ATD
clock frequencies, respectively?