Hardware Reference
In-Depth Information
Input Signal
V RL = 0 V
V RH = 5.12 V
Signed
8-bit
Codes
Unsigned
8-bit
Codes
Signed
10-bit
Codes
Unsigned
10-bit
Codes
5.120 V
5.100 V
5.080 V
7F
7F
7F
FF
FF
FE
7FC0
7F00
7E00
FFC0
FF00
FE00
2.580 V
2.560 V
2.540 V
01
00
FF
81
80
7F
0100
0000
FF00
8100
8000
7F00
0.020 V
0.000 V
81
80
01
00
8100
8000
0100
0000
Table 12.6 Left-justified, signed and unsigned ATD output codes
analog channel examined is specified by the channel selection code (CC, CB, and CA); sub-
sequent channels sampled in the sequence are determined by incrementing the channel
selection code.
ATD S TATUS R EGISTER 0 (ATD0STAT0, ATD1STAT0)
This read-only register contains the sequence complete flag, overrun flags for external trigger
and FIFO mode, and the conversion counter. The contents of this register are shown in Figure 12.13.
If the AFFC flag is set to 1, the SCF flag can be cleared by reading a result register. Other-
wise, it can be cleared by one of the following actions:
Writing a 1 to SCF
Writing to the ATD x CTL5 register (a new conversion is started)
7
6
5
4
3
2
1
0
CC2
CC0
SCF
0
ETORF
FIFOR
0
CC1
Reset:
0
0
0
0
0
0
0
0
SCF: sequence complete flag
0 = conversion sequence not completed.
1 = conversion sequence has completed.
ETORF: external trigger overrun flag
0 = no external trigger overrun has occurred.
1 = external trigger overrun has occurred.
FIFOR: FIFO overrun flag
0 = no overrun has occurred.
1 = an overrun has occurred.
CC2, CC1, CC0: conversion counter
The conversion counter points to the result register that will receive
the result of the current conversion.
In non-FIFO mode, this counter is reset to 0 at the begin and end of
the conversion.
In FIFO mode, this counter is not reset and will wrap around when
its maximum value is reached.
Figure 12.13 ATD status register 1 (ATD x STAT0, x 5 0 or 1)
 
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