Analog-to-Digital Converter - The HCS12/9S12: An Introduction to Software and Hardware Interfacing - page 599

E-clock

ATD clock

Clock
prescaler

Conversion
Complete interrupt

Mode and timing control

Results
ATD 0
ATD 1
ATD 2
ATD 3
ATD 4
ATD 5
ATD 6
ATD 7

V RH
V RL
V DDA
V SSA

Successive-
approximation
register (SAR)
and DAC

AN7/PAD7
AN6/PAD6
AN5/PAD5
AN4/PAD4
AN3/PAD3
AN2/PAD2
AN1/PAD1
AN0/PAD0

Sample and hold

+
-

1

1

Comparator

Analog
MUX

ATD input enable register

Port AD data register

Figure 12.8 ■ The HCS12 ATD block diagram

samples. When a sequence consists of multiple samples, the samples may be taken from one
channel or multiple channels. An interrupt may be generated on the completion of an A/D
conversion.
The analog multiplexer in Figure 12.8 selects one of the three internal or one of the external
signal sources for conversion. The sample selected by the multiplexer is amplified before charg-
ing the sample capacitor. The comparator indicates whether each successive output of the DAC
is higher or lower than the sampled input. The control registers and associated logic select the
conversion resolution, multiplexer input, and conversion sequencing mode, sample time, and
ADC clock cycle. Each result is available in three formats: right-justified unsigned, left-justified
signed, and left-justified unsigned.