Inter-Integrated Circuit (I2C) Interface - The HCS12/9S12: An Introduction to Software and Hardware Interfacing - page 581

11.8.5 Read Operation
24LC08B supports three types of read operations: current address read, random read, and
sequential read.
C URRENT A DDRESS R EAD
As explained earlier, the internal address counter is incremented by 1 after each access
(read or write). The current address read allows the master to read the byte immediately fol-
lowing the location accessed by the previous read or write operation. On receipt of the slave
address with the R/W bit set to 1, the 24LC08B issues an acknowledgement and transmits an
8-bit data byte. The master will not acknowledge the transfer but asserts a stop condition and
the 24LC08B discontinues transmission.
R ANDOM R EAD
Random read operations allow the master to access any memory location in a random man-
ner. To perform this type of read operation, the address of the memory location to be read must
be sent. The procedure for performing a random read is as follows:
Step 1
The master asserts a start condition and sends the control byte with the R/W bit set to 0
to the 24LC08B.
Step 2
The 24LC08B acknowledges the control byte.
Step 3
The master sends the address of the byte to be read to the 24LC08B.
Step 4
The 24LC08B acknowledges the byte address.
Step 5
The master asserts a repeated start condition.
Step 6
The master sends the control byte with R/W 5 1.
Step 7
The 24LC08B acknowledges the control byte and sends data to the master.
Step 8
The master asserts NACK to the 24LC08B.
Step 9
The master asserts the stop condition.
S EQUENTIAL R EAD
If the master acknowledges the data byte returned by the random read operation, the
24LC08B transmits the next sequentially addressed byte as long as the master provides the
clock signal on the SCL line. The master can read the whole chip using sequential read.