Hardware Reference
In-Depth Information
The I
2
C timing parameters are set by programming the I
2
C frequency divider register (IBFD).
The contents of this register are shown in Figure 11.26. The contents of this register are used to
prescale the bus clock for bit rate selection.
7
6
5
4
3
2
1
0
IBC7
IBC6
IBC5
IBC4
IBC3
IBC2
IBC1
IBC0
Figure 11.26
■
I
2
C frequency divider register (IBFD)
The use of these 8 bits is as follows:
•
IBC7,IBC6: multiply factor (shown in Table 11.3)
•
IBC5,IBC3: prescaler divider (shown in Table 11.4)
•
IBC2,IBC0: shift register tap points (shown in Table 11.5)
IBC7
,
IBC6
Multiply Factor
00
01
10
11
01
02
04
Reserved
Table 11.3
■
Multiply factor
scl2start
(clocks)
scl2stop
(clocks)
scl2tap
(clocks)
tap2tap
(clocks)
IBC5
,
IBC3
000
001
010
011
100
101
110
111
2
2
2
6
14
30
62
126
7
7
9
9
17
33
65
129
4
4
6
6
14
30
62
126
1
2
4
8
16
32
64
128
Table 11.4
■
Prescaler divider
SCL Tap
(clocks)
SDA Tap
(clocks)
IBC2
,
IBC0
000
001
010
011
100
101
110
111
5
6
7
8
9
10
12
15
1
1
2
2
3
3
4
4
Table 11.5
■
I
2
C bus tap and prescale values
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